Commit 5cebdea6 authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm-intel-next-fixes-2021-07-07' of... 

Merge tag 'drm-intel-next-fixes-2021-07-07' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

One fix targeting stable for display DP VSC, plus DG1 display fix and
a bug fix of IRQs usages and cleanup references to the DRM IRQ midlayer.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YOXDp/+CFDgJ2/7f@intel.com
parents 0d3a1b37 3dd6c11b

drivers/gpu/drm/i915/display/intel_ddi.c

+16 −3
Original line number Diff line number Diff line
@@ -1791,10 +1791,23 @@ static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 
{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	enum phy phy = intel_port_to_phy(i915, encoder->port);

	enum intel_dpll_id id;

	u32 val;



	return _cnl_ddi_get_pll(i915, DG1_DPCLKA_CFGCR0(phy),

				DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),

				DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));

	val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));

	val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);

	val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);

	id = val;



	/*

	 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A

	 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one

	 * bit for phy C and D.

	 */

	if (phy >= PHY_C)

		id += DPLL_ID_DG1_DPLL2;



	return intel_get_shared_dpll_by_id(i915, id);

}



static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,

drivers/gpu/drm/i915/display/intel_dp.c

+1 −1
Original line number Diff line number Diff line
@@ -2868,7 +2868,7 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, 
	if (size < sizeof(struct dp_sdp))

		return -EINVAL;



	memset(vsc, 0, size);

	memset(vsc, 0, sizeof(*vsc));



	if (sdp->sdp_header.HB0 != 0)

		return -EINVAL;

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+1 −1
Original line number Diff line number Diff line
@@ -1279,7 +1279,7 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine) 
		return true;



	/* Waiting to drain ELSP? */

	synchronize_hardirq(to_pci_dev(engine->i915->drm.dev)->irq);

	intel_synchronize_hardirq(engine->i915);

	intel_engine_flush_submission(engine);



	/* ELSP is empty, but there are ready requests? E.g. after reset */

drivers/gpu/drm/i915/gt/intel_ring_submission.c

+5 −2
Original line number Diff line number Diff line
@@ -184,8 +184,11 @@ static int xcs_resume(struct intel_engine_cs *engine) 
	ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n",

		     ring->head, ring->tail);



	/* Double check the ring is empty & disabled before we resume */

	synchronize_hardirq(engine->i915->drm.irq);

	/*

	 * Double check the ring is empty & disabled before we resume. Called

	 * from atomic context during PCI probe, so _hardirq().

	 */

	intel_synchronize_hardirq(engine->i915);

	if (!stop_ring(engine))

		goto err;

drivers/gpu/drm/i915/i915_drv.c

+0 −1
Original line number Diff line number Diff line
@@ -42,7 +42,6 @@ 
#include <drm/drm_aperture.h>

#include <drm/drm_atomic_helper.h>

#include <drm/drm_ioctl.h>

#include <drm/drm_irq.h>

#include <drm/drm_managed.h>

#include <drm/drm_probe_helper.h>