Commit 5ce5cef0 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2021-08-18' of... 

Merge tag 'drm-intel-fixes-2021-08-18' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- Expand a tweaked display workaround for all PCHs. (Anshuman)
- Fix eDP MSO pipe sanity checks for ADL-P. (Jani)
- Remove superfluous EXPORT_SYMBOL(). (Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YR137zkSAIbun1Ed@intel.com
parents b88aefc5 e3e86f41

drivers/gpu/drm/i915/display/intel_ddi.c

+12 −12
Original line number Diff line number Diff line
@@ -2463,6 +2463,15 @@ static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 
	}

}



/* Splitter enable for eDP MSO is limited to certain pipes. */

static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)

{

	if (IS_ALDERLAKE_P(i915))

		return BIT(PIPE_A) | BIT(PIPE_B);

	else

		return BIT(PIPE_A);

}



static void intel_ddi_mso_get_config(struct intel_encoder *encoder,

				     struct intel_crtc_state *pipe_config)

{
@@ -2480,8 +2489,7 @@ static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 
	if (!pipe_config->splitter.enable)

		return;



	/* Splitter enable is supported for pipe A only. */

	if (drm_WARN_ON(&i915->drm, pipe != PIPE_A)) {

	if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {

		pipe_config->splitter.enable = false;

		return;

	}
@@ -2513,10 +2521,6 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 
		return;



	if (crtc_state->splitter.enable) {

		/* Splitter enable is supported for pipe A only. */

		if (drm_WARN_ON(&i915->drm, pipe != PIPE_A))

			return;



		dss1 |= SPLITTER_ENABLE;

		dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);

		if (crtc_state->splitter.link_count == 2)
@@ -4743,12 +4747,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 


		dig_port->hpd_pulse = intel_dp_hpd_pulse;



		/* Splitter enable for eDP MSO is limited to certain pipes. */

		if (dig_port->dp.mso_link_count) {

			encoder->pipe_mask = BIT(PIPE_A);

			if (IS_ALDERLAKE_P(dev_priv))

				encoder->pipe_mask |= BIT(PIPE_B);

		}

		if (dig_port->dp.mso_link_count)

			encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);

	}



	/* In theory we don't need the encoder->type check, but leave it just in

drivers/gpu/drm/i915/display/intel_display_power.c

+8 −8
Original line number Diff line number Diff line
@@ -6387,13 +6387,13 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915) 
	if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||

	    IS_BROXTON(i915)) {

		bxt_enable_dc9(i915);

		/* Tweaked Wa_14010685332:icp,jsp,mcc */

		if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)

			intel_de_rmw(i915, SOUTH_CHICKEN1,

				     SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);

	} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {

		hsw_enable_pc8(i915);

	}



	/* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */

	if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)

		intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);

}



void intel_display_power_resume_early(struct drm_i915_private *i915)
@@ -6402,13 +6402,13 @@ void intel_display_power_resume_early(struct drm_i915_private *i915) 
	    IS_BROXTON(i915)) {

		gen9_sanitize_dc_state(i915);

		bxt_disable_dc9(i915);

		/* Tweaked Wa_14010685332:icp,jsp,mcc */

		if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)

			intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);



	} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {

		hsw_disable_pc8(i915);

	}



	/* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */

	if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)

		intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);

}



void intel_display_power_suspend(struct drm_i915_private *i915)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

+0 −1
Original line number Diff line number Diff line
@@ -206,7 +206,6 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) 


	return lttpr_count;

}

EXPORT_SYMBOL(intel_dp_init_lttpr_and_dprx_caps);



static u8 dp_voltage_max(u8 preemph)

{

drivers/gpu/drm/i915/i915_irq.c

+0 −21
Original line number Diff line number Diff line
@@ -3064,24 +3064,6 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv) 
	spin_unlock_irq(&dev_priv->irq_lock);

}



static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;



	/*

	 * Wa_14010685332:cnp/cmp,tgp,adp

	 * TODO: Clarify which platforms this applies to

	 * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as

	 * on earlier platforms and whether the workaround is also needed for runtime suspend/resume

	 */

	if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||

	    (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {

		intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,

				 SBCLK_RUN_REFCLK_DIS);

		intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);

	}

}



static void gen8_display_irq_reset(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3115,7 +3097,6 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv) 
	if (HAS_PCH_SPLIT(dev_priv))

		ibx_irq_reset(dev_priv);



	cnp_display_clock_wa(dev_priv);

}



static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3159,8 +3140,6 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) 


	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)

		GEN3_IRQ_RESET(uncore, SDE);



	cnp_display_clock_wa(dev_priv);

}



static void gen11_irq_reset(struct drm_i915_private *dev_priv)