Commit b88aefc5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'linux-5.14' of git://github.com/skeggsb/linux into drm-fixes 



- Ampere display fixes
- Fix longstanding MM race issue by removing unused code.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Ben Skeggs <skeggsb@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CACAvsv5jtUFkHsGe-pf-=RceDOgKygjPnCi=6d5vCLM_f5aeMQ@mail.gmail.com
parents e213bd1e 59f216cf

drivers/gpu/drm/nouveau/dispnv50/disp.c

+27 −0
Original line number Diff line number Diff line
@@ -2237,6 +2237,33 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 
		interlock[NV50_DISP_INTERLOCK_CORE] = 0;

	}



	/* Finish updating head(s)...

	 *

	 * NVD is rather picky about both where window assignments can change,

	 * *and* about certain core and window channel states matching.

	 *

	 * The EFI GOP driver on newer GPUs configures window channels with a

	 * different output format to what we do, and the core channel update

	 * in the assign_windows case above would result in a state mismatch.

	 *

	 * Delay some of the head update until after that point to workaround

	 * the issue.  This only affects the initial modeset.

	 *

	 * TODO: handle this better when adding flexible window mapping

	 */

	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {

		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);

		struct nv50_head *head = nv50_head(crtc);



		NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,

			  asyh->set.mask, asyh->clr.mask);



		if (asyh->set.mask) {

			nv50_head_flush_set_wndw(head, asyh);

			interlock[NV50_DISP_INTERLOCK_CORE] = 1;

		}

	}



	/* Update plane(s). */

	for_each_new_plane_in_state(state, plane, new_plane_state, i) {

		struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);

drivers/gpu/drm/nouveau/dispnv50/head.c

+9 −4
Original line number Diff line number Diff line
@@ -50,11 +50,8 @@ nv50_head_flush_clr(struct nv50_head *head, 
}



void

nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)

nv50_head_flush_set_wndw(struct nv50_head *head, struct nv50_head_atom *asyh)

{

	if (asyh->set.view   ) head->func->view    (head, asyh);

	if (asyh->set.mode   ) head->func->mode    (head, asyh);

	if (asyh->set.core   ) head->func->core_set(head, asyh);

	if (asyh->set.olut   ) {

		asyh->olut.offset = nv50_lut_load(&head->olut,

						  asyh->olut.buffer,
@@ -62,6 +59,14 @@ nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh) 
						  asyh->olut.load);

		head->func->olut_set(head, asyh);

	}

}



void

nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)

{

	if (asyh->set.view   ) head->func->view    (head, asyh);

	if (asyh->set.mode   ) head->func->mode    (head, asyh);

	if (asyh->set.core   ) head->func->core_set(head, asyh);

	if (asyh->set.curs   ) head->func->curs_set(head, asyh);

	if (asyh->set.base   ) head->func->base    (head, asyh);

	if (asyh->set.ovly   ) head->func->ovly    (head, asyh);

drivers/gpu/drm/nouveau/dispnv50/head.h

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ struct nv50_head { 


struct nv50_head *nv50_head_create(struct drm_device *, int index);

void nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh);

void nv50_head_flush_set_wndw(struct nv50_head *head, struct nv50_head_atom *asyh);

void nv50_head_flush_clr(struct nv50_head *head,

			 struct nv50_head_atom *asyh, bool flush);

drivers/gpu/drm/nouveau/include/nvif/cl0080.h

+2 −1
Original line number Diff line number Diff line
@@ -4,7 +4,8 @@ 


struct nv_device_v0 {

	__u8  version;

	__u8  pad01[7];

	__u8  priv;

	__u8  pad02[6];

	__u64 device;	/* device identifier, ~0 for client default */

};

drivers/gpu/drm/nouveau/include/nvif/class.h

+0 −2
Original line number Diff line number Diff line
@@ -61,8 +61,6 @@ 
#define NV10_CHANNEL_DMA                              /* cl506b.h */ 0x0000006e

#define NV17_CHANNEL_DMA                              /* cl506b.h */ 0x0000176e

#define NV40_CHANNEL_DMA                              /* cl506b.h */ 0x0000406e

#define NV50_CHANNEL_DMA                              /* cl506e.h */ 0x0000506e

#define G82_CHANNEL_DMA                               /* cl826e.h */ 0x0000826e



#define NV50_CHANNEL_GPFIFO                           /* cl506f.h */ 0x0000506f

#define G82_CHANNEL_GPFIFO                            /* cl826f.h */ 0x0000826f