Commit 593692d2 authored by Paul Hsieh's avatar Paul Hsieh Committed by Alex Deucher
Browse files

drm/amd/display: Power down hardware if timer not trigger 



[WHY]
In headless systems, if SetMode/Power down timer
is not called, hardware will not be powered down
causing HW/SW discrepancies. Powering down hardware
on SetPowerState to D3 will ensure SW/HW state is accurate.

[HOW]
1. If PowerDownThread timer is not trigger but OS call
SetPowerState to D3, power down hardware.
2. Update HDMI hang w/a to apply to all TMDS signals on
headless system

Reviewed-by: default avatarMartin Leung <Martin.Leung@amd.com>
Acked-by: default avatarPavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: default avatarPaul Hsieh <paul.hsieh@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 382aceb3

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

+14 −3
Original line number Diff line number Diff line
@@ -88,12 +88,23 @@ static int rn_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context) 


static void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)

{

	int display_count;

	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

	struct dc *dc = clk_mgr_base->ctx->dc;

	struct dc_state *context = dc->current_state;



	if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {



		display_count = rn_get_active_display_cnt_wa(dc, context);



		/* if we can go lower, go lower */

		if (display_count == 0) {

			rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);

			/* update power state */

			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;

		}

	}

}



static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

		struct dc_state *context, int ref_dpp_clk, bool safe_to_lower)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

+25 −1
Original line number Diff line number Diff line
@@ -615,13 +615,37 @@ static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk 
	}

}



void dcn31_set_low_power_state(struct clk_mgr *clk_mgr_base)

{

	int display_count;

	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

	struct dc *dc = clk_mgr_base->ctx->dc;

	struct dc_state *context = dc->current_state;



	if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {

		display_count = dcn31_get_active_display_cnt_wa(dc, context);

		/* if we can go lower, go lower */

		if (display_count == 0) {

			union display_idle_optimization_u idle_info = { 0 };



			idle_info.idle_info.df_request_disabled = 1;

			idle_info.idle_info.phy_ref_clk_off = 1;

			idle_info.idle_info.s0i2_rdy = 1;

			dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

			/* update power state */

			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;

		}

	}

}



static struct clk_mgr_funcs dcn31_funcs = {

	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,

	.update_clocks = dcn31_update_clocks,

	.init_clocks = dcn31_init_clocks,

	.enable_pme_wa = dcn31_enable_pme_wa,

	.are_clock_states_equal = dcn31_are_clock_states_equal,

	.notify_wm_ranges = dcn31_notify_wm_ranges

	.notify_wm_ranges = dcn31_notify_wm_ranges,

	.set_low_power_state = dcn31_set_low_power_state

};

extern struct clk_mgr_funcs dcn3_fpga_funcs;