Commit 382aceb3 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: remove dtbclk_ss compensation for dcn316 



[why]
dcn316's dtbclk is from non_ss clock source.
no compensation required here.

Reviewed-by: default avatarChris Park <Chris.Park@amd.com>
Acked-by: default avatarPavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent aa4be416

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

+1 −1
Original line number Diff line number Diff line
@@ -374,7 +374,7 @@ void dce_clock_read_ss_info(struct clk_mgr_internal *clk_mgr_dce) 
				clk_mgr_dce->dprefclk_ss_percentage =

						info.spread_spectrum_percentage;

			}

			if (clk_mgr_dce->base.ctx->dc->debug.ignore_dpref_ss)

			if (clk_mgr_dce->base.ctx->dc->config.ignore_dpref_ss)

				clk_mgr_dce->dprefclk_ss_percentage = 0;

		}

	}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

+2 −2
Original line number Diff line number Diff line
@@ -686,8 +686,8 @@ void dcn316_clk_mgr_construct( 
	clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base);

 	clk_mgr->base.dccg->ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;

	dce_clock_read_ss_info(&clk_mgr->base);

	clk_mgr->base.dccg->ref_dtbclk_khz =

	dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);

	/*clk_mgr->base.dccg->ref_dtbclk_khz =

	dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);*/



	clk_mgr->base.base.bw_params = &dcn316_bw_params;

drivers/gpu/drm/amd/display/dc/dc.h

+1 −1
Original line number Diff line number Diff line
@@ -340,6 +340,7 @@ struct dc_config { 
	bool is_asymmetric_memory;

	bool is_single_rank_dimm;

	bool use_pipe_ctx_sync_logic;

	bool ignore_dpref_ss;

};



enum visual_confirm {
@@ -729,7 +730,6 @@ struct dc_debug_options { 
	bool apply_vendor_specific_lttpr_wa;

	bool extended_blank_optimization;

	union aux_wake_wa_options aux_wake_wa;

	bool ignore_dpref_ss;

	uint8_t psr_power_use_phy_fsm;

};