Commit 5874d11c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.5-2023-06-30-1' of...

Merge tag 'amd-drm-fixes-6.5-2023-06-30-1' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-next

amd-drm-fixes-6.5-2023-06-30-1:

amdgpu:
- Misc cleanups
- GFX 9.4.3 fixes
- DEBUGFS build fix
- Fix LPDDR5 reporting
- ASPM fixes
- DCN 3.1.4 fixes
- DP MST fixes
- DCN 3.2.x fixes
- Display PSR TCON fixes
- SMU 13.x fixes
- RAS fixes
- Vega12/20 SMU fixes
- PSP flashing cleanup
- GFX9 MCBP fixes
- SR-IOV fixes
- GPUVM clear mappings fix for always valid BOs
- Add FAMS quirk for problematic monitor
- Fix possible UAF
- Better handle monentary temperature fluctuations
- SDMA 4.4.2 fixes
- Fencing fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230630175757.8128-1-alexander.deucher@amd.com
parents 67ebda8c 2e54154b
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+7 −3
Original line number Diff line number Diff line
@@ -286,6 +286,9 @@ extern int amdgpu_user_partt_mode;
#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)

/* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
#define AMDGPU_SWCTF_EXTRA_DELAY		50

struct amdgpu_xcp_mgr;
struct amdgpu_device;
struct amdgpu_irq_src;
@@ -1277,9 +1280,10 @@ int emu_soc_asic_init(struct amdgpu_device *adev);

#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));

#define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))
#define for_each_inst(i, inst_mask)        \
	for (i = ffs(inst_mask) - 1; inst_mask;                                \
	     inst_mask &= ~(1U << i), i = ffs(inst_mask) - 1)
	for (i = ffs(inst_mask); i-- != 0; \
	     i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))

#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))

+9 −0
Original line number Diff line number Diff line
@@ -1791,6 +1791,15 @@ const struct attribute_group amdgpu_vbios_version_attr_group = {
	.attrs = amdgpu_vbios_version_attrs
};

int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev)
{
	if (adev->mode_info.atom_context)
		return devm_device_add_group(adev->dev,
					     &amdgpu_vbios_version_attr_group);

	return 0;
}

/**
 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
 *
+1 −0
Original line number Diff line number Diff line
@@ -217,5 +217,6 @@ int amdgpu_atombios_get_data_table(struct amdgpu_device *adev,

void amdgpu_atombios_fini(struct amdgpu_device *adev);
int amdgpu_atombios_init(struct amdgpu_device *adev);
int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev);

#endif
+12 −6
Original line number Diff line number Diff line
@@ -327,10 +327,13 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
					mem_channel_number = igp_info->v11.umachannelnumber;
					if (!mem_channel_number)
						mem_channel_number = 1;
					/* channel width is 64 */
					if (vram_width)
						*vram_width = mem_channel_number * 64;
					mem_type = igp_info->v11.memorytype;
					if (mem_type == LpDdr5MemType)
						mem_channel_width = 32;
					else
						mem_channel_width = 64;
					if (vram_width)
						*vram_width = mem_channel_number * mem_channel_width;
					if (vram_type)
						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
					break;
@@ -345,10 +348,13 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
					mem_channel_number = igp_info->v21.umachannelnumber;
					if (!mem_channel_number)
						mem_channel_number = 1;
					/* channel width is 64 */
					if (vram_width)
						*vram_width = mem_channel_number * 64;
					mem_type = igp_info->v21.memorytype;
					if (mem_type == LpDdr5MemType)
						mem_channel_width = 32;
					else
						mem_channel_width = 64;
					if (vram_width)
						*vram_width = mem_channel_number * mem_channel_width;
					if (vram_type)
						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
					break;
+9 −8
Original line number Diff line number Diff line
@@ -136,9 +136,6 @@ static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p,
	bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
	p->uf_entry.priority = 0;
	p->uf_entry.tv.bo = &bo->tbo;
	/* One for TTM and two for the CS job */
	p->uf_entry.tv.num_shared = 3;

	drm_gem_object_put(gobj);

	size = amdgpu_bo_size(bo);
@@ -912,15 +909,19 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,

	mutex_lock(&p->bo_list->bo_list_mutex);

	/* One for TTM and one for the CS job */
	/* One for TTM and one for each CS job */
	amdgpu_bo_list_for_each_entry(e, p->bo_list)
		e->tv.num_shared = 2;
		e->tv.num_shared = 1 + p->gang_size;
	p->uf_entry.tv.num_shared = 1 + p->gang_size;

	amdgpu_bo_list_get_list(p->bo_list, &p->validated);

	INIT_LIST_HEAD(&duplicates);
	amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);

	/* Two for VM updates, one for TTM and one for each CS job */
	p->vm_pd.tv.num_shared = 3 + p->gang_size;

	if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
		list_add(&p->uf_entry.tv.head, &p->validated);

@@ -1653,15 +1654,15 @@ static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
			continue;

		r = dma_fence_wait_timeout(fence, true, timeout);
		if (r > 0 && fence->error)
			r = fence->error;

		dma_fence_put(fence);
		if (r < 0)
			return r;

		if (r == 0)
			break;

		if (fence->error)
			return fence->error;
	}

	memset(wait, 0, sizeof(*wait));
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