Commit 58390c8c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'iommu-updates-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu 

Pull iommu updates from Joerg Roedel:

 - Convert to platform remove callback returning void

 - Extend changing default domain to normal group

 - Intel VT-d updates:
     - Remove VT-d virtual command interface and IOASID
     - Allow the VT-d driver to support non-PRI IOPF
     - Remove PASID supervisor request support
     - Various small and misc cleanups

 - ARM SMMU updates:
     - Device-tree binding updates:
         * Allow Qualcomm GPU SMMUs to accept relevant clock properties
         * Document Qualcomm 8550 SoC as implementing an MMU-500
         * Favour new "qcom,smmu-500" binding for Adreno SMMUs

     - Fix S2CR quirk detection on non-architectural Qualcomm SMMU
       implementations

     - Acknowledge SMMUv3 PRI queue overflow when consuming events

     - Document (in a comment) why ATS is disabled for bypass streams

 - AMD IOMMU updates:
     - 5-level page-table support
     - NUMA awareness for memory allocations

 - Unisoc driver: Support for reattaching an existing domain

 - Rockchip driver: Add missing set_platform_dma_ops callback

 - Mediatek driver: Adjust the dma-ranges

 - Various other small fixes and cleanups

* tag 'iommu-updates-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (82 commits)
  iommu: Remove iommu_group_get_by_id()
  iommu: Make iommu_release_device() static
  iommu/vt-d: Remove BUG_ON in dmar_insert_dev_scope()
  iommu/vt-d: Remove a useless BUG_ON(dev->is_virtfn)
  iommu/vt-d: Remove BUG_ON in map/unmap()
  iommu/vt-d: Remove BUG_ON when domain->pgd is NULL
  iommu/vt-d: Remove BUG_ON in handling iotlb cache invalidation
  iommu/vt-d: Remove BUG_ON on checking valid pfn range
  iommu/vt-d: Make size of operands same in bitwise operations
  iommu/vt-d: Remove PASID supervisor request support
  iommu/vt-d: Use non-privileged mode for all PASIDs
  iommu/vt-d: Remove extern from function prototypes
  iommu/vt-d: Do not use GFP_ATOMIC when not needed
  iommu/vt-d: Remove unnecessary checks in iopf disabling path
  iommu/vt-d: Move PRI handling to IOPF feature path
  iommu/vt-d: Move pfsid and ats_qdep calculation to device probe path
  iommu/vt-d: Move iopf code from SVA to IOPF enabling path
  iommu/vt-d: Allow SVA with device-specific IOPF
  dmaengine: idxd: Add enable/disable device IOPF feature
  arm64: dts: mt8186: Add dma-ranges for the parent "soc" node
  ...
parents 7acc1372 e51b4198

Documentation/ABI/testing/sysfs-kernel-iommu_groups

+0 −1
Original line number Diff line number Diff line
@@ -53,7 +53,6 @@ Description: /sys/kernel/iommu_groups/<grp_id>/type shows the type of default 


		The default domain type of a group may be modified only when



		- The group has only one device.

		- The device in the group is not bound to any device driver.

		  So, the users must unbind the appropriate driver before

		  changing the default domain type.

Documentation/arch/x86/sva.rst

+1 −1
Original line number Diff line number Diff line
@@ -107,7 +107,7 @@ process share the same page tables, thus the same MSR value. 
PASID Life Cycle Management

===========================



PASID is initialized as INVALID_IOASID (-1) when a process is created.

PASID is initialized as IOMMU_PASID_INVALID (-1) when a process is created.



Only processes that access SVA-capable devices need to have a PASID

allocated. This allocation happens when a process opens/binds an SVA-capable

Documentation/devicetree/bindings/iommu/arm,smmu.yaml

+41 −4
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ properties: 
              - qcom,sm8250-smmu-500

              - qcom,sm8350-smmu-500

              - qcom,sm8450-smmu-500

              - qcom,sm8550-smmu-500

          - const: qcom,smmu-500

          - const: arm,mmu-500
@@ -75,9 +76,22 @@ properties: 
              - qcom,sm8350-smmu-500

              - qcom,sm8450-smmu-500

          - const: arm,mmu-500



      - description: Qcom Adreno GPUs implementing "arm,smmu-500"

      - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"

        items:

          - enum:

              - qcom,sc7280-smmu-500

              - qcom,sm6115-smmu-500

              - qcom,sm6125-smmu-500

              - qcom,sm8150-smmu-500

              - qcom,sm8250-smmu-500

              - qcom,sm8350-smmu-500

          - const: qcom,adreno-smmu

          - const: qcom,smmu-500

          - const: arm,mmu-500

      - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)

        deprecated: true

        items:

          # Do not add additional SoC to this list. Instead use previous list.

          - enum:

              - qcom,sc7280-smmu-500

              - qcom,sm8150-smmu-500
@@ -364,6 +378,30 @@ allOf: 
            - description: interface clock required to access smmu's registers

                through the TCU's programming interface.



  - if:

      properties:

        compatible:

          items:

            - enum:

                - qcom,sm6115-smmu-500

                - qcom,sm6125-smmu-500

            - const: qcom,adreno-smmu

            - const: qcom,smmu-500

            - const: arm,mmu-500

    then:

      properties:

        clock-names:

          items:

            - const: mem

            - const: hlos

            - const: iface



        clocks:

          items:

            - description: GPU memory bus clock

            - description: Voter clock required for HLOS SMMU access

            - description: Interface clock required for register access



  # Disallow clocks for all other platforms with specific compatibles

  - if:

      properties:
@@ -383,12 +421,11 @@ allOf: 
              - qcom,sdm845-smmu-500

              - qcom,sdx55-smmu-500

              - qcom,sdx65-smmu-500

              - qcom,sm6115-smmu-500

              - qcom,sm6125-smmu-500

              - qcom,sm6350-smmu-500

              - qcom,sm6375-smmu-500

              - qcom,sm8350-smmu-500

              - qcom,sm8450-smmu-500

              - qcom,sm8550-smmu-500

    then:

      properties:

        clock-names: false

Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml

+24 −8
Original line number Diff line number Diff line
@@ -74,16 +74,16 @@ properties: 
  renesas,ipmmu-main:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

      - minItems: 1

        items:

          - description: phandle to main IPMMU

          - description: the interrupt bit number associated with the particular

              cache IPMMU device. The interrupt bit number needs to match the main

              IPMMU IMSSTR register. Only used by cache IPMMU instances.

          - description:

              The interrupt bit number associated with the particular cache

              IPMMU device. If present, the interrupt bit number needs to match

              the main IPMMU IMSSTR register. Only used by cache IPMMU

              instances.

    description:

      Reference to the main IPMMU phandle plus 1 cell. The cell is

      the interrupt bit number associated with the particular cache IPMMU

      device. The interrupt bit number needs to match the main IPMMU IMSSTR

      register. Only used by cache IPMMU instances.

      Reference to the main IPMMU.



required:

  - compatible
@@ -109,6 +109,22 @@ allOf: 
      required:

        - power-domains



  - if:

      properties:

        compatible:

          contains:

            const: renesas,rcar-gen4-ipmmu-vmsa

    then:

      properties:

        renesas,ipmmu-main:

          items:

            - maxItems: 1

    else:

      properties:

        renesas,ipmmu-main:

          items:

            - minItems: 2



examples:

  - |

    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>

Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml

+0 −7
Original line number Diff line number Diff line
@@ -26,11 +26,6 @@ properties: 
      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.

      Ports are according to the HW.



  dma-ranges:

    maxItems: 1

    description: |

      Describes the physical address space of IOMMU maps to memory.



  "#address-cells":

    const: 2
@@ -89,7 +84,6 @@ required: 
  - compatible

  - power-domains

  - iommus

  - dma-ranges

  - ranges



additionalProperties: false
@@ -115,7 +109,6 @@ examples: 
                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,

                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,

                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;

            dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;

            #address-cells = <2>;

            #size-cells = <2>;

            ranges;