Commit 577f33bf authored by Borislav Petkov (AMD)'s avatar Borislav Petkov (AMD) Committed by Wenkuan Wang
Browse files

x86/CPU/AMD: Add X86_FEATURE_ZEN5 

mainline inclusion
from mainline-v6.8-rc2
commit 3e4147f33f8b647775357bae0248b9a2aeebfcd2
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I96RWV


CVE: NA

--------------------------------

Add a synthetic feature flag for Zen5.

Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20240104201138.5072-1-bp@alien8.de


Signed-off-by: default avatarWenkuan Wang <Wenkuan.Wang@amd.com>
parent 634a8eda

arch/x86/include/asm/cpufeatures.h

+1 −3
Original line number Diff line number Diff line
@@ -81,10 +81,8 @@ 
#define X86_FEATURE_K6_MTRR		( 3*32+ 1) /* AMD K6 nonstandard MTRRs */

#define X86_FEATURE_CYRIX_ARR		( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */

#define X86_FEATURE_CENTAUR_MCR		( 3*32+ 3) /* Centaur MCRs (= MTRRs) */



/* CPU types for specific tunings: */

#define X86_FEATURE_K8			( 3*32+ 4) /* "" Opteron, Athlon64 */

/* FREE, was #define X86_FEATURE_K7			( 3*32+ 5) "" Athlon */

#define X86_FEATURE_ZEN5		( 3*32+ 5) /* "" CPU based on Zen5 microarchitecture */

#define X86_FEATURE_P3			( 3*32+ 6) /* "" P3 */

#define X86_FEATURE_P4			( 3*32+ 7) /* "" P4 */

#define X86_FEATURE_CONSTANT_TSC	( 3*32+ 8) /* TSC ticks at a constant rate */

arch/x86/kernel/cpu/amd.c

+21 −4
Original line number Diff line number Diff line
@@ -542,7 +542,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) 


	/* Figure out Zen generations: */

	switch (c->x86) {

	case 0x17: {

	case 0x17:

		switch (c->x86_model) {

		case 0x00 ... 0x2f:

		case 0x50 ... 0x5f:
@@ -558,8 +558,8 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) 
			goto warn;

		}

		break;

	}

	case 0x19: {



	case 0x19:

		switch (c->x86_model) {

		case 0x00 ... 0x0f:

		case 0x20 ... 0x5f:
@@ -573,7 +573,17 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) 
			goto warn;

		}

		break;



	case 0x1a:

		switch (c->x86_model) {

		case 0x00 ... 0x0f:

			setup_force_cpu_cap(X86_FEATURE_ZEN5);

			break;

		default:

			goto warn;

		}

		break;



	default:

		break;

	}
@@ -1044,6 +1054,11 @@ static void init_amd_zen4(struct cpuinfo_x86 *c) 
		msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);

}



static void init_amd_zen5(struct cpuinfo_x86 *c)

{

	init_amd_zen_common();

}



static void init_amd(struct cpuinfo_x86 *c)

{

	early_init_amd(c);
@@ -1087,6 +1102,8 @@ static void init_amd(struct cpuinfo_x86 *c) 
		init_amd_zen3(c);

	else if (boot_cpu_has(X86_FEATURE_ZEN4))

		init_amd_zen4(c);

	else if (boot_cpu_has(X86_FEATURE_ZEN5))

		init_amd_zen5(c);



	/*

	 * Enable workaround for FXSAVE leak on CPUs