Commit 634a8eda authored by Borislav Petkov (AMD)'s avatar Borislav Petkov (AMD) Committed by Wenkuan Wang
Browse files

x86/CPU/AMD: Add X86_FEATURE_ZEN1 

mainline inclusion
from mainline-v6.8-rc1
commit 232afb557835d6f6859c73bf610bad308c96b131
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I96RWV


CVE: NA

--------------------------------

Add a synthetic feature flag specifically for first generation Zen
machines. There's need to have a generic flag for all Zen generations so
make X86_FEATURE_ZEN be that flag.

Fixes: 30fa92832f40 ("x86/CPU/AMD: Add ZenX generations flags")
Suggested-by: default avatarBrian Gerst <brgerst@gmail.com>
Suggested-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/dc3835e3-0731-4230-bbb9-336bbe3d042b@amd.com


Signed-off-by: default avatarWenkuan Wang <Wenkuan.Wang@amd.com>
parent 5dce4cd8

arch/x86/include/asm/cpufeatures.h

+2 −1
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ 
#define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */

#define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */

#define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */

#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU based on Zen microarchitecture */

#define X86_FEATURE_ZEN			( 7*32+28) /* "" Generic flag for all Zen and newer */

#define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */

#define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */

#define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
@@ -334,6 +334,7 @@ 
#define X86_FEATURE_ZEN2		(11*32+28) /* "" CPU based on Zen2 microarchitecture */

#define X86_FEATURE_ZEN3		(11*32+29) /* "" CPU based on Zen3 microarchitecture */

#define X86_FEATURE_ZEN4		(11*32+30) /* "" CPU based on Zen4 microarchitecture */

#define X86_FEATURE_ZEN1		(11*32+31) /* "" CPU based on Zen1 microarchitecture */



/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */

#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

arch/x86/kernel/cpu/amd.c

+6 −5
Original line number Diff line number Diff line
@@ -546,7 +546,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) 
		switch (c->x86_model) {

		case 0x00 ... 0x2f:

		case 0x50 ... 0x5f:

			setup_force_cpu_cap(X86_FEATURE_ZEN);

			setup_force_cpu_cap(X86_FEATURE_ZEN1);

			break;

		case 0x30 ... 0x4f:

		case 0x60 ... 0x7f:
@@ -952,12 +952,13 @@ void init_spectral_chicken(struct cpuinfo_x86 *c) 


static void init_amd_zen_common(void)

{

	setup_force_cpu_cap(X86_FEATURE_ZEN);

#ifdef CONFIG_NUMA

	node_reclaim_distance = 32;

#endif

}



static void init_amd_zen(struct cpuinfo_x86 *c)

static void init_amd_zen1(struct cpuinfo_x86 *c)

{

	init_amd_zen_common();

	fix_erratum_1386(c);
@@ -1078,8 +1079,8 @@ static void init_amd(struct cpuinfo_x86 *c) 
	case 0x16: init_amd_jg(c); break;

	}



	if (boot_cpu_has(X86_FEATURE_ZEN))

		init_amd_zen(c);

	if (boot_cpu_has(X86_FEATURE_ZEN1))

		init_amd_zen1(c);

	else if (boot_cpu_has(X86_FEATURE_ZEN2))

		init_amd_zen2(c);

	else if (boot_cpu_has(X86_FEATURE_ZEN3))
@@ -1138,7 +1139,7 @@ static void init_amd(struct cpuinfo_x86 *c) 
	 * Counter May Be Inaccurate".

	 */

	if (cpu_has(c, X86_FEATURE_IRPERF) &&

	    (boot_cpu_has(X86_FEATURE_ZEN) && c->x86_model > 0x2f))

	    (boot_cpu_has(X86_FEATURE_ZEN1) && c->x86_model > 0x2f))

		msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);



	check_null_seg_clears_base(c);

tools/arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -219,7 +219,7 @@ 
#define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */

#define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */

#define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */

#define X86_FEATURE_ZEN			(7*32+28) /* "" CPU based on Zen microarchitecture */

#define X86_FEATURE_ZEN			( 7*32+28) /* "" Generic flag for all Zen and newer */

#define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */

#define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */

#define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */