Commit 5763d7f2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2022-09-16' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "This is the regular drm fixes pull.

  The i915 and misc fixes are fairly regular, but the amdgpu contains
  fixes for new hw blocks, the dcn314 specific path hookups and also has
  a bunch of fixes for clang stack size warnings which are a bit churny
  but fairly straightforward. This means it looks a little larger than
  usual.

  amdgpu:
   - BACO fixes for some RDNA2 boards
   - PCI AER fixes uncovered by a core PCI change
   - Properly hook up dirtyfb helper
   - RAS fixes for GC 11.x
   - TMR fix
   - DCN 3.2.x fixes
   - DCN 3.1.4 fixes
   - LLVM DML stack size fixes

  i915:
   - Revert a display patch around max DP source rate now that the
     proper WaEdpLinkRateDataReload is in place
   - Fix perf limit reasons bit position
   - Fix unclaimmed mmio registers on suspend flow with GuC
   - A vma_move_to_active fix for a regression with video decoding
   - DP DSP fix

  gma500:
   - Locking and IRQ fixes

  meson:
   - OSD1 display fixes

  panel-edp:
   - Fix Innolux timings

  rockchip:
   - DP/HDMI fixes"

* tag 'drm-fixes-2022-09-16' of git://anongit.freedesktop.org/drm/drm: (42 commits)
  drm/amdgpu: make sure to init common IP before gmc
  drm/amdgpu: move nbio sdma_doorbell_range() into sdma code for vega
  drm/amdgpu: move nbio ih_doorbell_range() into ih code for vega
  drm/rockchip: Fix return type of cdn_dp_connector_mode_valid
  drm/amd/display: Mark dml30's UseMinimumDCFCLK() as noinline for stack usage
  drm/amd/display: Reduce number of arguments of dml31's CalculateFlipSchedule()
  drm/amd/display: Reduce number of arguments of dml31's CalculateWatermarksAndDRAMSpeedChangeSupport()
  drm/amd/display: Reduce number of arguments of dml32_CalculatePrefetchSchedule()
  drm/amd/display: Reduce number of arguments of dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
  drm/amd/display: Refactor SubVP calculation to remove FPU
  drm/amd/display: Limit user regamma to a valid value
  drm/amd/display: add workaround for subvp cursor corruption for DCN32/321
  drm/amd/display: SW cursor fallback for SubVP
  drm/amd/display: Round cursor width up for MALL allocation
  drm/amd/display: Correct dram channel width for dcn314
  drm/amd/display: Relax swizzle checks for video non-RGB formats on DCN314
  drm/amd/display: Hook up DCN314 specific dml implementation
  drm/amd/display: Enable dlg and vba compilation for dcn314
  drm/amd/display: Fix compilation errors on DCN314
  drm/amd/display: Fix divide by zero in DML
  ...
parents 714820c6 25100377

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+11 −3
Original line number Diff line number Diff line
@@ -2365,8 +2365,16 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) 
		}

		adev->ip_blocks[i].status.sw = true;



		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {

			/* need to do common hw init early so everything is set up for gmc */

			r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);

			if (r) {

				DRM_ERROR("hw_init %d failed %d\n", i, r);

				goto init_failed;

			}

			adev->ip_blocks[i].status.hw = true;

		} else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {

			/* need to do gmc hw init early so we can allocate gpu mem */

		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {

			/* Try to reserve bad pages early */

			if (amdgpu_sriov_vf(adev))

				amdgpu_virt_exchange_data(adev);
@@ -3052,8 +3060,8 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) 
	int i, r;



	static enum amd_ip_block_type ip_order[] = {

		AMD_IP_BLOCK_TYPE_GMC,

		AMD_IP_BLOCK_TYPE_COMMON,

		AMD_IP_BLOCK_TYPE_GMC,

		AMD_IP_BLOCK_TYPE_PSP,

		AMD_IP_BLOCK_TYPE_IH,

	};

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

+2 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 
#include <linux/pci.h>

#include <linux/pm_runtime.h>

#include <drm/drm_crtc_helper.h>

#include <drm/drm_damage_helper.h>

#include <drm/drm_edid.h>

#include <drm/drm_gem_framebuffer_helper.h>

#include <drm/drm_fb_helper.h>
@@ -496,6 +497,7 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 
static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {

	.destroy = drm_gem_fb_destroy,

	.create_handle = drm_gem_fb_create_handle,

	.dirty = drm_atomic_helper_dirtyfb,

};



uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+1 −1
Original line number Diff line number Diff line
@@ -756,7 +756,7 @@ static int psp_tmr_init(struct psp_context *psp) 
	}



	pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;

	ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),

	ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT,

				      AMDGPU_GEM_DOMAIN_VRAM,

				      &psp->tmr_bo, &psp->tmr_mc_addr, pptr);

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 
#define PSP_CMD_BUFFER_SIZE	0x1000

#define PSP_1_MEG		0x100000

#define PSP_TMR_SIZE(adev)	((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)

#define PSP_TMR_ALIGNMENT	0x100000

#define PSP_FW_NAME_LEN		0x24



enum psp_shared_mem_size {

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+2 −1
Original line number Diff line number Diff line
@@ -1811,7 +1811,8 @@ static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) 
		amdgpu_ras_query_error_status(adev, &info);



		if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&

		    adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {

		    adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) &&

		    adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) {

			if (amdgpu_ras_reset_error_status(adev, info.head.block))

				dev_warn(adev->dev, "Failed to reset error counter and error status");

		}