Commit 25100377 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2022-09-15' of... 

Merge tag 'drm-intel-fixes-2022-09-15' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- Revert a display patch around max DP source rate now
  that the proper WaEdpLinkRateDataReload is in place. (Ville)
- Fix perf limit reasons bit position. (Ashutosh)
- Fix unclaimmed mmio registers on suspend flow with GuC. (Umesh)
- A vma_move_to_active fix for a regression with video decoding. (Nirmoy)
- DP DSP fix. (Ankit)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YyMtmGMXRLsURoM5@intel.com
parents 87d9862b 8787f6fa

drivers/gpu/drm/i915/display/icl_dsi.c

+2 −0
Original line number Diff line number Diff line
@@ -1629,6 +1629,8 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 
	/* FIXME: initialize from VBT */

	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;



	vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;



	ret = intel_dsc_compute_params(crtc_state);

	if (ret)

		return ret;

drivers/gpu/drm/i915/display/intel_dp.c

+4 −29
Original line number Diff line number Diff line
@@ -389,23 +389,13 @@ static int dg2_max_source_rate(struct intel_dp *intel_dp) 
	return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;

}



static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)

{

	u32 voltage;



	voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK;



	return voltage == VOLTAGE_INFO_0_85V;

}



static int icl_max_source_rate(struct intel_dp *intel_dp)

{

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);

	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);



	if (intel_phy_is_combo(dev_priv, phy) &&

	    (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))

	if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))

		return 540000;



	return 810000;
@@ -413,23 +403,7 @@ static int icl_max_source_rate(struct intel_dp *intel_dp) 


static int ehl_max_source_rate(struct intel_dp *intel_dp)

{

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);

	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);



	if (intel_dp_is_edp(intel_dp) || is_low_voltage_sku(dev_priv, phy))

		return 540000;



	return 810000;

}



static int dg1_max_source_rate(struct intel_dp *intel_dp)

{

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);

	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);



	if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))

	if (intel_dp_is_edp(intel_dp))

		return 540000;



	return 810000;
@@ -491,7 +465,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) 
			max_rate = dg2_max_source_rate(intel_dp);

		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||

			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))

			max_rate = dg1_max_source_rate(intel_dp);

			max_rate = 810000;

		else if (IS_JSL_EHL(dev_priv))

			max_rate = ehl_max_source_rate(intel_dp);

		else
@@ -1395,6 +1369,7 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, 
	 * DP_DSC_RC_BUF_SIZE for this.

	 */

	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;

	vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;



	/*

	 * Slice Height of 8 works for all currently available panels. So start

drivers/gpu/drm/i915/display/intel_vdsc.c

+0 −1
Original line number Diff line number Diff line
@@ -460,7 +460,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) 
	u8 i = 0;



	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;

	vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;

	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,

					     pipe_config->dsc.slice_count);

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

+6 −1
Original line number Diff line number Diff line
@@ -1438,7 +1438,12 @@ void intel_guc_busyness_park(struct intel_gt *gt) 
	if (!guc_submission_initialized(guc))

		return;



	cancel_delayed_work(&guc->timestamp.work);

	/*

	 * There is a race with suspend flow where the worker runs after suspend

	 * and causes an unclaimed register access warning. Cancel the worker

	 * synchronously here.

	 */

	cancel_delayed_work_sync(&guc->timestamp.work);



	/*

	 * Before parking, we should sample engine busyness stats if we need to.

drivers/gpu/drm/i915/i915_reg.h

+8 −8
Original line number Diff line number Diff line
@@ -1857,14 +1857,14 @@ 


#define GT0_PERF_LIMIT_REASONS		_MMIO(0x1381a8)

#define   GT0_PERF_LIMIT_REASONS_MASK	0xde3

#define   PROCHOT_MASK			REG_BIT(1)

#define   THERMAL_LIMIT_MASK		REG_BIT(2)

#define   RATL_MASK			REG_BIT(6)

#define   VR_THERMALERT_MASK		REG_BIT(7)

#define   VR_TDC_MASK			REG_BIT(8)

#define   POWER_LIMIT_4_MASK		REG_BIT(9)

#define   POWER_LIMIT_1_MASK		REG_BIT(11)

#define   POWER_LIMIT_2_MASK		REG_BIT(12)

#define   PROCHOT_MASK			REG_BIT(0)

#define   THERMAL_LIMIT_MASK		REG_BIT(1)

#define   RATL_MASK			REG_BIT(5)

#define   VR_THERMALERT_MASK		REG_BIT(6)

#define   VR_TDC_MASK			REG_BIT(7)

#define   POWER_LIMIT_4_MASK		REG_BIT(8)

#define   POWER_LIMIT_1_MASK		REG_BIT(10)

#define   POWER_LIMIT_2_MASK		REG_BIT(11)



#define CHV_CLK_CTL1			_MMIO(0x101100)

#define VLV_CLK_CTL2			_MMIO(0x101104)