Commit 5620b4b0 authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas
Browse files

arm64/sysreg: Standardise naming for ID_AA64PFR0_EL1.AdvSIMD constants 



The architecture refers to the register field identifying advanced SIMD as
AdvSIMD but the kernel refers to it as ASIMD. Use the architecture's
naming. No functional changes.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarKristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-15-broonie@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 4f8456c3

arch/arm64/include/asm/sysreg.h

+2 −2
Original line number Diff line number Diff line
@@ -695,7 +695,7 @@ 
#define ID_AA64PFR0_EL1_SVE_SHIFT		32

#define ID_AA64PFR0_EL1_RAS_SHIFT		28

#define ID_AA64PFR0_EL1_GIC_SHIFT		24

#define ID_AA64PFR0_EL1_ASIMD_SHIFT		20

#define ID_AA64PFR0_EL1_AdvSIMD_SHIFT		20

#define ID_AA64PFR0_EL1_FP_SHIFT		16

#define ID_AA64PFR0_EL1_EL3_SHIFT		12

#define ID_AA64PFR0_EL1_EL2_SHIFT		8
@@ -708,7 +708,7 @@ 
#define ID_AA64PFR0_EL1_RAS_V1P1		0x2

#define ID_AA64PFR0_EL1_FP_NI			0xf

#define ID_AA64PFR0_EL1_FP_IMP			0x0

#define ID_AA64PFR0_EL1_ASIMD_NI		0xf

#define ID_AA64PFR0_EL1_AdvSIMD_NI		0xf

#define ID_AA64PFR0_EL1_ELx_64BIT_ONLY		0x1

#define ID_AA64PFR0_EL1_ELx_32BIT_64BIT		0x2

arch/arm64/kernel/cpufeature.c

+3 −3
Original line number Diff line number Diff line
@@ -253,7 +253,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 
				   FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0),

	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_ASIMD_SHIFT, 4, ID_AA64PFR0_EL1_ASIMD_NI),

	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI),

	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0),
@@ -2710,8 +2710,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_ASIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_ASIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),

arch/arm64/kvm/hyp/include/nvhe/fixed_config.h

+1 −1
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ 
 */

#define PVM_ID_AA64PFR0_ALLOW (\

	ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP) | \

	ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_ASIMD) | \

	ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD) | \

	ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_DIT) \

	)

arch/arm64/kvm/hyp/nvhe/pkvm.c

+1 −1
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu) 
	 */

	BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP),

				PVM_ID_AA64PFR0_ALLOW));

	BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_ASIMD),

	BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD),

				PVM_ID_AA64PFR0_ALLOW));



	/* Trap RAS unless all current versions are supported */