Commit 4f8456c3 authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas
Browse files

arm64/sysreg: Standardise naming for ID_AA64PFR0_EL1 constants 



We generally refer to the baseline feature implemented as _IMP so in
preparation for automatic generation of register defines update those for
ID_AA64PFR0_EL1 to reflect this.

In the case of ASIMD we don't actually use the define so just remove it.

No functional changes.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarKristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-14-broonie@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent ca951862

arch/arm64/include/asm/sysreg.h

+4 −5
Original line number Diff line number Diff line
@@ -702,14 +702,13 @@ 
#define ID_AA64PFR0_EL1_EL1_SHIFT		4

#define ID_AA64PFR0_EL1_EL0_SHIFT		0



#define ID_AA64PFR0_EL1_AMU			0x1

#define ID_AA64PFR0_EL1_SVE			0x1

#define ID_AA64PFR0_EL1_RAS_V1			0x1

#define ID_AA64PFR0_EL1_AMU_IMP			0x1

#define ID_AA64PFR0_EL1_SVE_IMP			0x1

#define ID_AA64PFR0_EL1_RAS_IMP			0x1

#define ID_AA64PFR0_EL1_RAS_V1P1		0x2

#define ID_AA64PFR0_EL1_FP_NI			0xf

#define ID_AA64PFR0_EL1_FP_SUPPORTED		0x0

#define ID_AA64PFR0_EL1_FP_IMP			0x0

#define ID_AA64PFR0_EL1_ASIMD_NI		0xf

#define ID_AA64PFR0_EL1_ASIMD_SUPPORTED		0x0

#define ID_AA64PFR0_EL1_ELx_64BIT_ONLY		0x1

#define ID_AA64PFR0_EL1_ELx_32BIT_64BIT		0x2

arch/arm64/kernel/cpufeature.c

+4 −4
Original line number Diff line number Diff line
@@ -2246,7 +2246,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64PFR0_EL1_SVE_SHIFT,

		.field_width = 4,

		.min_field_value = ID_AA64PFR0_EL1_SVE,

		.min_field_value = ID_AA64PFR0_EL1_SVE_IMP,

		.matches = has_cpuid_feature,

		.cpu_enable = sve_kernel_enable,

	},
@@ -2261,7 +2261,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64PFR0_EL1_RAS_SHIFT,

		.field_width = 4,

		.min_field_value = ID_AA64PFR0_EL1_RAS_V1,

		.min_field_value = ID_AA64PFR0_EL1_RAS_IMP,

		.cpu_enable = cpu_clear_disr,

	},

#endif /* CONFIG_ARM64_RAS_EXTN */
@@ -2280,7 +2280,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64PFR0_EL1_AMU_SHIFT,

		.field_width = 4,

		.min_field_value = ID_AA64PFR0_EL1_AMU,

		.min_field_value = ID_AA64PFR0_EL1_AMU_IMP,

		.cpu_enable = cpu_amu_enable,

	},

#endif /* CONFIG_ARM64_AMU_EXTN */
@@ -2727,7 +2727,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),

	HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_EL1_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),

#ifdef CONFIG_ARM64_SVE

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_EL1_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_EL1_SVE_IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),

	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),

	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),

	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),

arch/arm64/kvm/hyp/include/nvhe/fixed_config.h

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ 
	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \

	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL2), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \

	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL3), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \

	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), ID_AA64PFR0_EL1_RAS_V1) \

	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), ID_AA64PFR0_EL1_RAS_IMP) \

	)



/*