Commit 554836cc authored by Yifan Zha's avatar Yifan Zha Committed by Alex Deucher
Browse files

drm/amdgpu: Add MES KIQ clear to tell RLC that KIQ is dequeued 



[Why]
As MES KIQ is dequeued, tell RLC that KIQ is inactive

[How]
Clear the RLC_CP_SCHEDULERS Active bit which RLC checks KIQ status
In addition, driver can halt MES under SRIOV when unloading driver

v2:
Use scheduler0 mask to clear KIQ portion of RLC_CP_SCHEDULERS

Signed-off-by: default avatarYifan Zha <Yifan.Zha@amd.com>
Reviewed-by: default avatarHorace Chen <horace.chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a2a0bdf1

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+12 −2
Original line number Diff line number Diff line
@@ -1138,6 +1138,16 @@ static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 
	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);

}



static void mes_v11_0_kiq_clear(struct amdgpu_device *adev)

{

	uint32_t tmp;



	/* tell RLC which is KIQ dequeue */

	tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);

	tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK;

	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);

}



static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)

{

	int r = 0;
@@ -1182,9 +1192,9 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 


	if (amdgpu_sriov_vf(adev)) {

		mes_v11_0_kiq_dequeue(&adev->gfx.kiq.ring);

		mes_v11_0_kiq_clear(adev);

	}



	if (!amdgpu_sriov_vf(adev))

	mes_v11_0_enable(adev, false);



	return 0;