Commit a2a0bdf1 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: add dscclk instance offset check 



[why]
based on dscclk instance offset check conditiona program dscclk

Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d170e938

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h

+8 −0
Original line number Original line Diff line number Diff line
@@ -205,6 +205,11 @@ 
	type PHYDSYMCLK_GATE_DISABLE; \

	type PHYDSYMCLK_GATE_DISABLE; \

	type PHYESYMCLK_GATE_DISABLE;

	type PHYESYMCLK_GATE_DISABLE;





#define DCCG314_REG_FIELD_LIST(type) \

	type DSCCLK3_DTO_PHASE;\

	type DSCCLK3_DTO_MODULO;\

	type DSCCLK3_DTO_ENABLE;



#define DCCG32_REG_FIELD_LIST(type) \

#define DCCG32_REG_FIELD_LIST(type) \

	type DPSTREAMCLK0_EN;\

	type DPSTREAMCLK0_EN;\

	type DPSTREAMCLK1_EN;\

	type DPSTREAMCLK1_EN;\
@@ -237,6 +242,7 @@ struct dccg_shift { 
	DCCG_REG_FIELD_LIST(uint8_t)

	DCCG_REG_FIELD_LIST(uint8_t)

	DCCG3_REG_FIELD_LIST(uint8_t)

	DCCG3_REG_FIELD_LIST(uint8_t)

	DCCG31_REG_FIELD_LIST(uint8_t)

	DCCG31_REG_FIELD_LIST(uint8_t)

	DCCG314_REG_FIELD_LIST(uint8_t)

	DCCG32_REG_FIELD_LIST(uint8_t)

	DCCG32_REG_FIELD_LIST(uint8_t)

};

};
@@ -244,6 +250,7 @@ struct dccg_mask { 
	DCCG_REG_FIELD_LIST(uint32_t)

	DCCG_REG_FIELD_LIST(uint32_t)

	DCCG3_REG_FIELD_LIST(uint32_t)

	DCCG3_REG_FIELD_LIST(uint32_t)

	DCCG31_REG_FIELD_LIST(uint32_t)

	DCCG31_REG_FIELD_LIST(uint32_t)

	DCCG314_REG_FIELD_LIST(uint32_t)

	DCCG32_REG_FIELD_LIST(uint32_t)

	DCCG32_REG_FIELD_LIST(uint32_t)

};

};
@@ -273,6 +280,7 @@ struct dccg_registers { 
	uint32_t DSCCLK0_DTO_PARAM;

	uint32_t DSCCLK0_DTO_PARAM;

	uint32_t DSCCLK1_DTO_PARAM;

	uint32_t DSCCLK1_DTO_PARAM;

	uint32_t DSCCLK2_DTO_PARAM;

	uint32_t DSCCLK2_DTO_PARAM;

	uint32_t DSCCLK3_DTO_PARAM;

	uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;

	uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;

	uint32_t DPSTREAMCLK_GATE_DISABLE;

	uint32_t DPSTREAMCLK_GATE_DISABLE;

	uint32_t DCCG_GATE_DISABLE_CNTL;

	uint32_t DCCG_GATE_DISABLE_CNTL;

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c

+18 −0
Original line number Original line Diff line number Diff line
@@ -360,6 +360,15 @@ void dccg31_disable_dscclk(struct dccg *dccg, int inst) 
				DSCCLK2_DTO_PHASE, 0,

				DSCCLK2_DTO_PHASE, 0,

				DSCCLK2_DTO_MODULO, 1);

				DSCCLK2_DTO_MODULO, 1);

		break;

		break;

	case 3:

		if (REG(DSCCLK3_DTO_PARAM)) {

			REG_UPDATE(DSCCLK_DTO_CTRL,

					DSCCLK3_DTO_ENABLE, 1);

			REG_UPDATE_2(DSCCLK3_DTO_PARAM,

					DSCCLK3_DTO_PHASE, 0,

					DSCCLK3_DTO_MODULO, 1);

		}

		break;

	default:

	default:

		BREAK_TO_DEBUGGER();

		BREAK_TO_DEBUGGER();

		return;

		return;
@@ -395,6 +404,15 @@ void dccg31_enable_dscclk(struct dccg *dccg, int inst) 
		REG_UPDATE(DSCCLK_DTO_CTRL,

		REG_UPDATE(DSCCLK_DTO_CTRL,

				DSCCLK2_DTO_ENABLE, 0);

				DSCCLK2_DTO_ENABLE, 0);

		break;

		break;

	case 3:

		if (REG(DSCCLK3_DTO_PARAM)) {

			REG_UPDATE(DSCCLK_DTO_CTRL,

					DSCCLK3_DTO_ENABLE, 0);

			REG_UPDATE_2(DSCCLK3_DTO_PARAM,

					DSCCLK3_DTO_PHASE, 0,

					DSCCLK3_DTO_MODULO, 0);

		}

		break;

	default:

	default:

		BREAK_TO_DEBUGGER();

		BREAK_TO_DEBUGGER();

		return;

		return;

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -68,6 +68,7 @@ 
	SR(DSCCLK0_DTO_PARAM),\

	SR(DSCCLK0_DTO_PARAM),\

	SR(DSCCLK1_DTO_PARAM),\

	SR(DSCCLK1_DTO_PARAM),\

	SR(DSCCLK2_DTO_PARAM),\

	SR(DSCCLK2_DTO_PARAM),\

	SR(DSCCLK3_DTO_PARAM),\

	SR(DSCCLK_DTO_CTRL),\

	SR(DSCCLK_DTO_CTRL),\

	SR(DCCG_GATE_DISABLE_CNTL2),\

	SR(DCCG_GATE_DISABLE_CNTL2),\

	SR(DCCG_GATE_DISABLE_CNTL3),\

	SR(DCCG_GATE_DISABLE_CNTL3),\
@@ -149,6 +150,8 @@ 
	DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\

	DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\

	DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\

	DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\

	DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\

	DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\

	DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, mask_sh),\

	DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_MODULO, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
@@ -184,6 +187,7 @@ 
	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, mask_sh),\

	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, mask_sh),\

	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, mask_sh),\

	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, mask_sh),\

	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh),\

	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh),\

	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK3_DTO_ENABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\