Commit 5536e735 authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Felix Fietkau
Browse files

mt76: mt7921: introduce mt7921_dma_{enable,disable} utilities 



Introduce mt7921_dma_enable and mt7921_dma_disable utilities routine in
order for code reusing between mt7921_dma_reset and mt7921_dma_init.
This is a preliminary patch to reset dma during device driver_own
request.

Signed-off-by: default avatarSean Wang <sean.wang@mediatek.com>
Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent fcad15d5

drivers/net/wireless/mediatek/mt76/mt7921/dma.c

+35 −73
Original line number Diff line number Diff line
@@ -221,18 +221,8 @@ static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 
	return dev->bus_ops->rmw(mdev, addr, mask, val);

}



static int mt7921_dmashdl_disabled(struct mt7921_dev *dev)

static int mt7921_dma_disable(struct mt7921_dev *dev, bool force)

{

	mt76_clear(dev, MT_WFDMA0_GLO_CFG_EXT0, MT_WFDMA0_CSR_TX_DMASHDL_ENABLE);

	mt76_set(dev, MT_DMASHDL_SW_CONTROL, MT_DMASHDL_DMASHDL_BYPASS);



	return 0;

}



static int mt7921_dma_reset(struct mt7921_dev *dev, bool force)

{

	int i;



	if (force) {

		/* reset */

		mt76_clear(dev, MT_WFDMA0_RST,
@@ -244,6 +234,11 @@ static int mt7921_dma_reset(struct mt7921_dev *dev, bool force) 
			 MT_WFDMA0_RST_LOGIC_RST);

	}



	/* disable dmashdl */

	mt76_clear(dev, MT_WFDMA0_GLO_CFG_EXT0,

		   MT_WFDMA0_CSR_TX_DMASHDL_ENABLE);

	mt76_set(dev, MT_DMASHDL_SW_CONTROL, MT_DMASHDL_DMASHDL_BYPASS);



	/* disable WFDMA0 */

	mt76_clear(dev, MT_WFDMA0_GLO_CFG,

		   MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN |
@@ -257,18 +252,11 @@ static int mt7921_dma_reset(struct mt7921_dev *dev, bool force) 
		       MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000))

		return -ETIMEDOUT;



	/* reset hw queues */

	for (i = 0; i < __MT_TXQ_MAX; i++)

		mt76_queue_reset(dev, dev->mphy.q_tx[i]);



	for (i = 0; i < __MT_MCUQ_MAX; i++)

		mt76_queue_reset(dev, dev->mt76.q_mcu[i]);



	mt76_for_each_q_rx(&dev->mt76, i)

		mt76_queue_reset(dev, &dev->mt76.q_rx[i]);



	mt76_tx_status_check(&dev->mt76, NULL, true);

	return 0;

}



static int mt7921_dma_enable(struct mt7921_dev *dev)

{

	/* configure perfetch settings */

	mt7921_dma_prefetch(dev);
@@ -300,6 +288,29 @@ static int mt7921_dma_reset(struct mt7921_dev *dev, bool force) 
	return 0;

}



static int mt7921_dma_reset(struct mt7921_dev *dev, bool force)

{

	int i, err;



	err = mt7921_dma_disable(dev, force);

	if (err)

		return err;



	/* reset hw queues */

	for (i = 0; i < __MT_TXQ_MAX; i++)

		mt76_queue_reset(dev, dev->mphy.q_tx[i]);



	for (i = 0; i < __MT_MCUQ_MAX; i++)

		mt76_queue_reset(dev, dev->mt76.q_mcu[i]);



	mt76_for_each_q_rx(&dev->mt76, i)

		mt76_queue_reset(dev, &dev->mt76.q_rx[i]);



	mt76_tx_status_check(&dev->mt76, NULL, true);



	return mt7921_dma_enable(dev);

}



int mt7921_wfsys_reset(struct mt7921_dev *dev)

{

	mt76_set(dev, 0x70002600, BIT(0));
@@ -362,32 +373,10 @@ int mt7921_dma_init(struct mt7921_dev *dev) 


	mt76_dma_attach(&dev->mt76);



	/* reset */

	mt76_clear(dev, MT_WFDMA0_RST,

		   MT_WFDMA0_RST_DMASHDL_ALL_RST |

		   MT_WFDMA0_RST_LOGIC_RST);



	mt76_set(dev, MT_WFDMA0_RST,

		 MT_WFDMA0_RST_DMASHDL_ALL_RST |

		 MT_WFDMA0_RST_LOGIC_RST);



	ret = mt7921_dmashdl_disabled(dev);

	ret = mt7921_dma_disable(dev, true);

	if (ret)

		return ret;



	/* disable WFDMA0 */

	mt76_clear(dev, MT_WFDMA0_GLO_CFG,

		   MT_WFDMA0_GLO_CFG_TX_DMA_EN |

		   MT_WFDMA0_GLO_CFG_RX_DMA_EN |

		   MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |

		   MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |

		   MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |

		   MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);



	mt76_poll(dev, MT_WFDMA0_GLO_CFG,

		  MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |

		  MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);



	/* init tx queue */

	ret = mt7921_init_tx_queues(&dev->phy, MT7921_TXQ_BAND0,

				    MT7921_TX_RING_SIZE);
@@ -439,34 +428,7 @@ int mt7921_dma_init(struct mt7921_dev *dev) 
			  mt7921_poll_tx, NAPI_POLL_WEIGHT);

	napi_enable(&dev->mt76.tx_napi);



	/* configure perfetch settings */

	mt7921_dma_prefetch(dev);



	/* reset dma idx */

	mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);



	/* configure delay interrupt */

	mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);



	mt76_set(dev, MT_WFDMA0_GLO_CFG,

		 MT_WFDMA0_GLO_CFG_TX_WB_DDONE |

		 MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN |

		 MT_WFDMA0_GLO_CFG_CLK_GAT_DIS |

		 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |

		 MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |

		 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);



	mt76_set(dev, MT_WFDMA0_GLO_CFG,

		 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);



	mt76_set(dev, MT_WFDMA_DUMMY_CR, MT_WFDMA_NEED_REINIT);



	/* enable interrupts for TX/RX rings */

	mt7921_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |

			  MT_INT_MCU_CMD);

	mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);



	return 0;

	return mt7921_dma_enable(dev);

}



void mt7921_dma_cleanup(struct mt7921_dev *dev)