Loading arch/arc/kernel/irq.c +7 −3 Original line number Diff line number Diff line Loading @@ -39,10 +39,14 @@ void arc_init_IRQ(void) level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5; level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6; if (level_mask) { pr_info("Level-2 interrupts bitset %x\n", level_mask); /* * Write to register, even if no LV2 IRQs configured to reset it * in case bootloader had mucked with it */ write_aux_reg(AUX_IRQ_LEV, level_mask); } if (level_mask) pr_info("Level-2 interrupts bitset %x\n", level_mask); } /* Loading Loading
arch/arc/kernel/irq.c +7 −3 Original line number Diff line number Diff line Loading @@ -39,10 +39,14 @@ void arc_init_IRQ(void) level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5; level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6; if (level_mask) { pr_info("Level-2 interrupts bitset %x\n", level_mask); /* * Write to register, even if no LV2 IRQs configured to reset it * in case bootloader had mucked with it */ write_aux_reg(AUX_IRQ_LEV, level_mask); } if (level_mask) pr_info("Level-2 interrupts bitset %x\n", level_mask); } /* Loading