Commit 539bf218 authored Jan 26, 2021 by Lee Jones Committed by Stephen Boyd Feb 10, 2021

clk: ti: dpll3xxx: Fix some kernel-doc headers and promote other worthy ones

Fixes the following W=1 kernel build warning(s):

drivers/clk/ti/dpll3xxx.c:414: warning: Function parameter or member 'hw' not described in 'omap3_dpll_recalc'
drivers/clk/ti/dpll3xxx.c:414: warning: Function parameter or member 'parent_rate' not described in 'omap3_dpll_recalc'
drivers/clk/ti/dpll3xxx.c:414: warning: Excess function parameter 'clk' description in 'omap3_dpll_recalc'
drivers/clk/ti/dpll3xxx.c:437: warning: Function parameter or member 'hw' not described in 'omap3_noncore_dpll_enable'
drivers/clk/ti/dpll3xxx.c:437: warning: Excess function parameter 'clk' description in 'omap3_noncore_dpll_enable'
drivers/clk/ti/dpll3xxx.c:479: warning: Function parameter or member 'hw' not described in 'omap3_noncore_dpll_disable'
drivers/clk/ti/dpll3xxx.c:479: warning: Excess function parameter 'clk' description in 'omap3_noncore_dpll_disable'
drivers/clk/ti/dpll3xxx.c:755: warning: Function parameter or member 'hw' not described in 'omap3_clkoutx2_recalc'
drivers/clk/ti/dpll3xxx.c:755: warning: Function parameter or member 'parent_rate' not described in 'omap3_clkoutx2_recalc'
drivers/clk/ti/dpll3xxx.c:755: warning: Excess function parameter 'clk' description in 'omap3_clkoutx2_recalc'

Cc: Tero Kristo <kristo@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-omap@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-4-lee.jones@linaro.org

Reviewed-by: Tero Kristo <kristo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent ed1b7dd7

drivers/clk/ti/dpll3xxx.c

+11 −9

Original line number	Diff line number	Diff line
		@@ -125,7 +125,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
		return f;
		}

		/*
		/**
		* _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
		* @clk: pointer to a DPLL struct clk
		*
		@@ -168,7 +168,7 @@ static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
		return r;
		}

		/*
		/**
		* _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
		* @clk: pointer to a DPLL struct clk
		*
		@@ -204,7 +204,7 @@ static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
		return r;
		}

		/*
		/**
		* _omap3_noncore_dpll_stop - instruct a DPLL to stop
		* @clk: pointer to a DPLL struct clk
		*
		@@ -291,7 +291,7 @@ static void _lookup_sddiv(struct clk_hw_omap clk, u8 sd_div, u16 m, u8 n)
		*sd_div = sd;
		}

		/*
		/**
		* _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
		* @clk: struct clk * of DPLL to set
		* @freqsel: FREQSEL value to set
		@@ -406,7 +406,8 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)

		/**
		* omap3_dpll_recalc - recalculate DPLL rate
		* @clk: DPLL struct clk
		* @hw: struct clk_hw containing the DPLL struct clk
		* @parent_rate: clock rate of the DPLL parent
		*
		* Recalculate and propagate the DPLL rate.
		*/
		@@ -421,7 +422,7 @@ unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)

		/**
		* omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
		* @clk: pointer to a DPLL struct clk
		* @hw: struct clk_hw containing then pointer to a DPLL struct clk
		*
		* Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
		* The choice of modes depends on the DPLL's programmed rate: if it is
		@@ -470,7 +471,7 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw)

		/**
		* omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
		* @clk: pointer to a DPLL struct clk
		* @hw: struct clk_hw containing then pointer to a DPLL struct clk
		*
		* Instructs a non-CORE DPLL to enter low-power stop. This function is
		* intended for use in struct clkops. No return value.
		@@ -745,7 +746,8 @@ static struct clk_hw_omap omap3_find_clkoutx2_dpll(struct clk_hw hw)

		/**
		* omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
		* @clk: DPLL output struct clk
		* @hw: pointer struct clk_hw
		* @parent_rate: clock rate of the DPLL parent
		*
		* Using parent clock DPLL data, look up DPLL state. If locked, set our
		* rate to the dpll_clk * 2; otherwise, just use dpll_clk.
		@@ -913,7 +915,7 @@ const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
		* omap3_dpll4_set_rate - set rate for omap3 per-dpll
		* @hw: clock to change
		* @rate: target rate for clock
		* @parent_rate: rate of the parent clock
		* @parent_rate: clock rate of the DPLL parent
		*
		* Check if the current SoC supports the per-dpll reprogram operation
		* or not, and then do the rate change if supported. Returns -EINVAL