Commit ed1b7dd7 authored Jan 26, 2021 by Lee Jones Committed by Stephen Boyd Feb 10, 2021

clk: ti: clkt_dpll: Fix some kernel-doc misdemeanours



Fixes the following W=1 kernel build warning(s):

 drivers/clk/ti/clkt_dpll.c:284: warning: Function parameter or member 'hw' not described in 'omap2_dpll_round_rate'
 drivers/clk/ti/clkt_dpll.c:284: warning: Function parameter or member 'parent_rate' not described in 'omap2_dpll_round_rate'
 drivers/clk/ti/clkt_dpll.c:284: warning: Excess function parameter 'clk' description in 'omap2_dpll_round_rate'

Cc: Tero Kristo <kristo@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: linux-omap@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-3-lee.jones@linaro.org


Reviewed-by: Tero Kristo <kristo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent bc22d596

drivers/clk/ti/clkt_dpll.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -269,8 +269,9 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)

		/**
		* omap2_dpll_round_rate - round a target rate for an OMAP DPLL
		* @clk: struct clk * for a DPLL
		* @hw: struct clk_hw containing the struct clk * for a DPLL
		* @target_rate: desired DPLL clock rate
		* @parent_rate: parent's DPLL clock rate
		*
		* Given a DPLL and a desired target rate, round the target rate to a
		* possible, programmable rate for this DPLL. Attempts to select the