Unverified Commit 527f4090 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!781 Intel: backport split lock EMR CPU support for OLK 5.10 

Merge Pull Request from: @etzhao 
 
Hi,

Bus lock detection EMR CPU support for OpenEuler backporting was tested Okay, help to review and merge

Title: bus lock detection and ratelimit feature for OpenEuler.

Passed test cases
No function change.
#dmesg 
 see
 [    0.000000] x86/split lock detection: #AC: crashing the kernel on kernel split_locks and warning on user-space split_locks
#cat /proc/cpuinfo |grep split 
 split_lock_detect
 
Known issue:
No

Default config change:
No

Thanks,
Ethan 
 
Link:https://gitee.com/openeuler/kernel/pulls/781

 

Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Reviewed-by: default avatarAichun Shi <aichun.shi@intel.com>
Reviewed-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 92b03342 fd31bbc9

arch/x86/kernel/cpu/intel.c

+22 −36
Original line number Diff line number Diff line
@@ -1387,30 +1387,13 @@ void switch_to_sld(unsigned long tifn) 
}



/*

 * Bits in the IA32_CORE_CAPABILITIES are not architectural, so they should

 * only be trusted if it is confirmed that a CPU model implements a

 * specific feature at a particular bit position.

 *

 * The possible driver data field values:

 *

 * - 0: CPU models that are known to have the per-core split-lock detection

 * CPU models that are known to have the per-core split-lock detection

 * feature even though they do not enumerate IA32_CORE_CAPABILITIES.

 *

 * - 1: CPU models which may enumerate IA32_CORE_CAPABILITIES and if so use

 *      bit 5 to enumerate the per-core split-lock detection feature.

 */

static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X,	0),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,	0),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,	0),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,	1),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	1),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,	1),

	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,		1),

	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		1),

	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	1),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		1),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		1),

	{}

};
@@ -1422,24 +1405,27 @@ static void __init split_lock_setup(struct cpuinfo_x86 *c) 
	if (boot_cpu_has(X86_FEATURE_HYPERVISOR))

		return;



	/* Check for CPUs that have support but do not enumerate it: */

	m = x86_match_cpu(split_lock_cpu_ids);

	if (!m)

		return;

	if (m)

		goto supported;



	switch (m->driver_data) {

	case 0:

		break;

	case 1:

	if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES))

		return;



	/*

	 * Not all bits in MSR_IA32_CORE_CAPS are architectural, but

	 * MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT is.  All CPUs that set

	 * it have split lock detection.

	 */

	rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps);

		if (!(ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT))

			return;

		break;

	default:

	if (ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT)

		goto supported;



	/* CPU is not in the model list and does not have the MSR bit: */

	return;

	}



supported:

	cpu_model_supports_sld = true;

	__split_lock_setup();

}