x86/split_lock: Enumerate architectural split lock disable bit

mainline inclusion
from mainline-v6.4-rc1
commit d7ce15e1
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I73RWZ


CVE: NA

Reference: NA

---------------------------------------------------------------

Intel-SIG: commit d7ce15e1 x86/split_lock: Enumerate architectural split lock disable bit
Backport for EMR platform splitlock support.

The December 2022 edition of the Intel Instruction Set Extensions manual
defined that the split lock disable bit in the IA32_CORE_CAPABILITIES MSR
is (and retrospectively always has been) architectural.

Remove all the model specific checks except for Ice Lake variants which are
still needed because these CPU models do not enumerate presence of the
IA32_CORE_CAPABILITIES MSR.

Originally-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/lkml/20220701131958.687066-1-fenghua.yu@intel.com/t/#mada243bee0915532a6adef6a9e32d244d1a9aef4


(cherry picked from commit d7ce15e1)
Signed-off-by: Ethan Zhao <haifeng.zhao@linux.intel.com>