Commit fd31bbc9 authored by Fenghua Yu's avatar Fenghua Yu Committed by Ethan Zhao
Browse files

x86/split_lock: Enumerate architectural split lock disable bit 

mainline inclusion
from mainline-v6.4-rc1
commit d7ce15e1
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I73RWZ


CVE: NA

Reference: NA

---------------------------------------------------------------

Intel-SIG: commit d7ce15e1 x86/split_lock: Enumerate architectural split lock disable bit
Backport for EMR platform splitlock support.

The December 2022 edition of the Intel Instruction Set Extensions manual
defined that the split lock disable bit in the IA32_CORE_CAPABILITIES MSR
is (and retrospectively always has been) architectural.

Remove all the model specific checks except for Ice Lake variants which are
still needed because these CPU models do not enumerate presence of the
IA32_CORE_CAPABILITIES MSR.

Originally-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: default avatarFenghua Yu <fenghua.yu@intel.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarTony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/lkml/20220701131958.687066-1-fenghua.yu@intel.com/t/#mada243bee0915532a6adef6a9e32d244d1a9aef4


(cherry picked from commit d7ce15e1)
Signed-off-by: default avatarEthan Zhao <haifeng.zhao@linux.intel.com>
parent 213e8d25

arch/x86/kernel/cpu/intel.c

+22 −36
Original line number Diff line number Diff line
@@ -1387,30 +1387,13 @@ void switch_to_sld(unsigned long tifn) 
}



/*

 * Bits in the IA32_CORE_CAPABILITIES are not architectural, so they should

 * only be trusted if it is confirmed that a CPU model implements a

 * specific feature at a particular bit position.

 *

 * The possible driver data field values:

 *

 * - 0: CPU models that are known to have the per-core split-lock detection

 * CPU models that are known to have the per-core split-lock detection

 * feature even though they do not enumerate IA32_CORE_CAPABILITIES.

 *

 * - 1: CPU models which may enumerate IA32_CORE_CAPABILITIES and if so use

 *      bit 5 to enumerate the per-core split-lock detection feature.

 */

static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X,	0),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,	0),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,	0),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,	1),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	1),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,	1),

	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,		1),

	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		1),

	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	1),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		1),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		1),

	{}

};
@@ -1422,24 +1405,27 @@ static void __init split_lock_setup(struct cpuinfo_x86 *c) 
	if (boot_cpu_has(X86_FEATURE_HYPERVISOR))

		return;



	/* Check for CPUs that have support but do not enumerate it: */

	m = x86_match_cpu(split_lock_cpu_ids);

	if (!m)

		return;

	if (m)

		goto supported;



	switch (m->driver_data) {

	case 0:

		break;

	case 1:

	if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES))

		return;



	/*

	 * Not all bits in MSR_IA32_CORE_CAPS are architectural, but

	 * MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT is.  All CPUs that set

	 * it have split lock detection.

	 */

	rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps);

		if (!(ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT))

			return;

		break;

	default:

	if (ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT)

		goto supported;



	/* CPU is not in the model list and does not have the MSR bit: */

	return;

	}



supported:

	cpu_model_supports_sld = true;

	__split_lock_setup();

}