Unverified Commit 50724efc authored by Andy Chiu's avatar Andy Chiu Committed by Palmer Dabbelt
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riscv: hwcap: change ELF_HWCAP to a function



Using a function is flexible to represent ELF_HWCAP. So the kernel may
encode hwcap reflecting supported hardware features just at the moment of
the start of each program.

This will be helpful when we introduce prctl/sysctl interface to control
per-process availability of Vector extension in following patches.
Programs started with V disabled should see V masked off in theirs
ELF_HWCAP.

Signed-off-by: default avatarAndy Chiu <andy.chiu@sifive.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230605110724.21391-21-andy.chiu@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 0f4b8257
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+1 −1
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ extern bool compat_elf_check_arch(Elf32_Ehdr *hdr);
 * via a bitmap that coorespends to each single-letter ISA extension.  This is
 * essentially defunct, but will remain for compatibility with userspace.
 */
#define ELF_HWCAP	(elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1))
#define ELF_HWCAP	riscv_get_elf_hwcap()
extern unsigned long elf_hwcap;

/*
+2 −0
Original line number Diff line number Diff line
@@ -61,6 +61,8 @@

#include <linux/jump_label.h>

unsigned long riscv_get_elf_hwcap(void);

struct riscv_isa_ext_data {
	/* Name of the extension displayed to userspace via /proc/cpuinfo */
	char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
+5 −0
Original line number Diff line number Diff line
@@ -293,6 +293,11 @@ void __init riscv_fill_hwcap(void)
	pr_info("riscv: ELF capabilities %s\n", print_str);
}

unsigned long riscv_get_elf_hwcap(void)
{
	return (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1));
}

#ifdef CONFIG_RISCV_ALTERNATIVE
/*
 * Alternative patch sites consider 48 bits when determining when to patch