Unverified Commit 0f4b8257 authored by Vincent Chen's avatar Vincent Chen Committed by Palmer Dabbelt
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riscv: KVM: Add vector lazy save/restore support 



This patch adds vector context save/restore for guest VCPUs. To reduce the
impact on KVM performance, the implementation imitates the FP context
switch mechanism to lazily store and restore the vector context only when
the kernel enters/exits the in-kernel run loop and not during the KVM
world switch.

Signed-off-by: default avatarVincent Chen <vincent.chen@sifive.com>
Signed-off-by: default avatarGreentime Hu <greentime.hu@sifive.com>
Signed-off-by: default avatarAndy Chiu <andy.chiu@sifive.com>
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Acked-by: default avatarAnup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20230605110724.21391-20-andy.chiu@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent bf78f1ea

arch/riscv/include/asm/kvm_host.h

+2 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/spinlock.h>

#include <asm/hwcap.h>

#include <asm/kvm_aia.h>

#include <asm/ptrace.h>

#include <asm/kvm_vcpu_fp.h>

#include <asm/kvm_vcpu_insn.h>

#include <asm/kvm_vcpu_sbi.h>
@@ -145,6 +146,7 @@ struct kvm_cpu_context { 
	unsigned long sstatus;

	unsigned long hstatus;

	union __riscv_fp_state fp;

	struct __riscv_v_ext_state vector;

};



struct kvm_vcpu_csr {

arch/riscv/include/asm/kvm_vcpu_vector.h

0 → 100644
+82 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (C) 2022 SiFive

 *

 * Authors:

 *     Vincent Chen <vincent.chen@sifive.com>

 *     Greentime Hu <greentime.hu@sifive.com>

 */



#ifndef __KVM_VCPU_RISCV_VECTOR_H

#define __KVM_VCPU_RISCV_VECTOR_H



#include <linux/types.h>



#ifdef CONFIG_RISCV_ISA_V

#include <asm/vector.h>

#include <asm/kvm_host.h>



static __always_inline void __kvm_riscv_vector_save(struct kvm_cpu_context *context)

{

	__riscv_v_vstate_save(&context->vector, context->vector.datap);

}



static __always_inline void __kvm_riscv_vector_restore(struct kvm_cpu_context *context)

{

	__riscv_v_vstate_restore(&context->vector, context->vector.datap);

}



void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu);

void kvm_riscv_vcpu_guest_vector_save(struct kvm_cpu_context *cntx,

				      unsigned long *isa);

void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_context *cntx,

					 unsigned long *isa);

void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context *cntx);

void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_context *cntx);

int kvm_riscv_vcpu_alloc_vector_context(struct kvm_vcpu *vcpu,

					struct kvm_cpu_context *cntx);

void kvm_riscv_vcpu_free_vector_context(struct kvm_vcpu *vcpu);

#else



struct kvm_cpu_context;



static inline void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu)

{

}



static inline void kvm_riscv_vcpu_guest_vector_save(struct kvm_cpu_context *cntx,

						    unsigned long *isa)

{

}



static inline void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_context *cntx,

						       unsigned long *isa)

{

}



static inline void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context *cntx)

{

}



static inline void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_context *cntx)

{

}



static inline int kvm_riscv_vcpu_alloc_vector_context(struct kvm_vcpu *vcpu,

						      struct kvm_cpu_context *cntx)

{

	return 0;

}



static inline void kvm_riscv_vcpu_free_vector_context(struct kvm_vcpu *vcpu)

{

}

#endif



int kvm_riscv_vcpu_get_reg_vector(struct kvm_vcpu *vcpu,

				  const struct kvm_one_reg *reg,

				  unsigned long rtype);

int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu,

				  const struct kvm_one_reg *reg,

				  unsigned long rtype);

#endif

arch/riscv/include/uapi/asm/kvm.h

+7 −0
Original line number Diff line number Diff line
@@ -204,6 +204,13 @@ enum KVM_RISCV_SBI_EXT_ID { 
#define KVM_REG_RISCV_SBI_MULTI_REG_LAST	\

		KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1)



/* V extension registers are mapped as type 9 */

#define KVM_REG_RISCV_VECTOR		(0x09 << KVM_REG_RISCV_TYPE_SHIFT)

#define KVM_REG_RISCV_VECTOR_CSR_REG(name)	\

		(offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long))

#define KVM_REG_RISCV_VECTOR_REG(n)	\

		((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))



#endif



#endif /* __LINUX_KVM_RISCV_H */

arch/riscv/kvm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ kvm-y += mmu.o 
kvm-y += vcpu.o

kvm-y += vcpu_exit.o

kvm-y += vcpu_fp.o

kvm-y += vcpu_vector.o

kvm-y += vcpu_insn.o

kvm-y += vcpu_switch.o

kvm-y += vcpu_sbi.o

arch/riscv/kvm/vcpu.c

+22 −0
Original line number Diff line number Diff line
@@ -22,6 +22,8 @@ 
#include <asm/cacheflush.h>

#include <asm/hwcap.h>

#include <asm/sbi.h>

#include <asm/vector.h>

#include <asm/kvm_vcpu_vector.h>



const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {

	KVM_GENERIC_VCPU_STATS(),
@@ -139,6 +141,8 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) 


	kvm_riscv_vcpu_fp_reset(vcpu);



	kvm_riscv_vcpu_vector_reset(vcpu);



	kvm_riscv_vcpu_timer_reset(vcpu);



	kvm_riscv_vcpu_aia_reset(vcpu);
@@ -199,6 +203,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 
	cntx->hstatus |= HSTATUS_SPVP;

	cntx->hstatus |= HSTATUS_SPV;



	if (kvm_riscv_vcpu_alloc_vector_context(vcpu, cntx))

		return -ENOMEM;



	/* By default, make CY, TM, and IR counters accessible in VU mode */

	reset_csr->scounteren = 0x7;
@@ -242,6 +249,9 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 


	/* Free unused pages pre-allocated for G-stage page table mappings */

	kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache);



	/* Free vector context space for host and guest kernel */

	kvm_riscv_vcpu_free_vector_context(vcpu);

}



int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
@@ -680,6 +690,9 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, 
		return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);

	case KVM_REG_RISCV_SBI_EXT:

		return kvm_riscv_vcpu_set_reg_sbi_ext(vcpu, reg);

	case KVM_REG_RISCV_VECTOR:

		return kvm_riscv_vcpu_set_reg_vector(vcpu, reg,

						 KVM_REG_RISCV_VECTOR);

	default:

		break;

	}
@@ -709,6 +722,9 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, 
		return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg);

	case KVM_REG_RISCV_SBI_EXT:

		return kvm_riscv_vcpu_get_reg_sbi_ext(vcpu, reg);

	case KVM_REG_RISCV_VECTOR:

		return kvm_riscv_vcpu_get_reg_vector(vcpu, reg,

						 KVM_REG_RISCV_VECTOR);

	default:

		break;

	}
@@ -1003,6 +1019,9 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 
	kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context);

	kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context,

					vcpu->arch.isa);

	kvm_riscv_vcpu_host_vector_save(&vcpu->arch.host_context);

	kvm_riscv_vcpu_guest_vector_restore(&vcpu->arch.guest_context,

					    vcpu->arch.isa);



	kvm_riscv_vcpu_aia_load(vcpu, cpu);
@@ -1022,6 +1041,9 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 
	kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context);



	kvm_riscv_vcpu_timer_save(vcpu);

	kvm_riscv_vcpu_guest_vector_save(&vcpu->arch.guest_context,

					 vcpu->arch.isa);

	kvm_riscv_vcpu_host_vector_restore(&vcpu->arch.host_context);



	csr->vsstatus = csr_read(CSR_VSSTATUS);

	csr->vsie = csr_read(CSR_VSIE);