Commit 4e683604 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Controller 



Add clock and reset entries for SPI Multi I/O Bus Controller.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-2-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 67f80edf

drivers/clk/renesas/r9a07g043-cpg.c

+18 −0
Original line number Diff line number Diff line
@@ -28,9 +28,13 @@ enum clk_ids { 
	CLK_PLL2_DIV2,

	CLK_PLL2_DIV2_8,

	CLK_PLL3,

	CLK_PLL3_400,

	CLK_PLL3_533,

	CLK_PLL3_DIV2,

	CLK_PLL3_DIV2_4,

	CLK_PLL3_DIV2_4_2,

	CLK_SEL_PLL3_3,

	CLK_DIV_PLL3_C,

	CLK_PLL5,

	CLK_PLL5_500,

	CLK_PLL5_250,
@@ -67,6 +71,7 @@ static const struct clk_div_table dtable_1_32[] = { 
};



/* Mux clock tables */

static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };

static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };

static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
@@ -89,6 +94,12 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { 
	DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),

	DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),

	DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),

	DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),

	DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),

	DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,

		sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),

	DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,

		DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),

	DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),

	DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6),

	DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2),
@@ -110,6 +121,8 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { 
	DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),

	DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2,

		sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),

	DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),

	DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),

	DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0,

		   sel_shdi, ARRAY_SIZE(sel_shdi)),

	DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1,
@@ -143,6 +156,10 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 
				0x548, 4),

	DEF_MOD("wdt2_clk",	R9A07G043_WDT2_CLK, R9A07G043_OSCCLK,

				0x548, 5),

	DEF_MOD("spi_clk2",	R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,

				0x550, 0),

	DEF_MOD("spi_clk",	R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,

				0x550, 1),

	DEF_MOD("sdhi0_imclk",	R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4,

				0x554, 0),

	DEF_MOD("sdhi0_imclk2",	R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4,
@@ -230,6 +247,7 @@ static struct rzg2l_reset r9a07g043_resets[] = { 
	DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),

	DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),

	DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2),

	DEF_RST(R9A07G043_SPI_RST, 0x850, 0),

	DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),

	DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),

	DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),