Commit 67f80edf authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g044: Add DSI clock and reset entries 



Add DSI clock and reset entries to CPG driver.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-10-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 6f6178f1

drivers/clk/renesas/r9a07g044-cpg.c

+16 −1
Original line number Diff line number Diff line
@@ -194,7 +194,7 @@ static const struct { 
};



static const struct {

	struct rzg2l_mod_clk common[65];

	struct rzg2l_mod_clk common[71];

#ifdef CONFIG_CLK_R9A07G054

	struct rzg2l_mod_clk drp[0];

#endif
@@ -254,6 +254,18 @@ static const struct { 
					0x558, 1),

		DEF_MOD("gpu_ace_clk",	R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,

					0x558, 2),

		DEF_MOD("dsi_pll_clk",	R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,

					0x568, 0),

		DEF_MOD("dsi_sys_clk",	R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,

					0x568, 1),

		DEF_MOD("dsi_aclk",	R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1,

					0x568, 2),

		DEF_MOD("dsi_pclk",	R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2,

					0x568, 3),

		DEF_MOD("dsi_vclk",	R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3,

					0x568, 4),

		DEF_MOD("dsi_lpclk",	R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4,

					0x568, 5),

		DEF_COUPLED("lcdc_a",	R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0,

					0x56c, 0),

		DEF_COUPLED("lcdc_p",	R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT,
@@ -355,6 +367,9 @@ static struct rzg2l_reset r9a07g044_resets[] = { 
	DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),

	DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),

	DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),

	DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),

	DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),

	DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),

	DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0),

	DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),

	DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),