arm64: Add MIDR encoding for HiSilicon Taishan CPUs

ascend inclusion
category: feature
bugzilla: 46922, https://gitee.com/openeuler/kernel/issues/I41AUQ


CVE: NA

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Adding the MIDR encodings for HiSilicon Taishan v200 CPUs,
which is used in Kunpeng ARM64 server SoCs. TSV200 is the
abbreviation of Taishan v200. There are two variants of
TSV200, variant 0 and variant 1.

Signed-off-by: Weilong Chen <chenweilong@huawei.com>
Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Reviewed-by: Ding Tianhong <dingtianhong@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: Xie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: Cheng Jian <cj.chengjian@huawei.com>