Commit 4d5c4ae3 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-socfpga', 'clk-mstar', 'clk-qcom' and 'clk-warnings' into clk-next 

 - PLL support on MStar/SigmaStar ARMv7 SoCs
 - CPU clks for Qualcomm SDX55
 - GCC and RPMh clks for Qualcomm SC8180x and SC7280 SoCs
 - GCC clks for Qualcomm SM8350
 - Video clk fixups on Qualcomm SM8250
 - GPU clks for Qualcomm SDM660/SDM630
 - Improvements for multimedia clks on Qualcomm MSM8998
 - Fix many warnings with W=1 enabled builds under drivers/clk/

* clk-socfpga:
  clk: socfpga: agilex: add clock driver for eASIC N5X platform
  dt-bindings: documentation: add clock bindings information for eASIC N5X

* clk-mstar:
  clk: mstar: msc313-mpll: Fix format specifier
  clk: mstar: Allow MStar clk drivers to be compile tested
  clk: mstar: MStar/SigmaStar MPLL driver
  clk: fixed: add devm helper for clk_hw_register_fixed_factor()
  dt-bindings: clk: mstar msc313 mpll binding description
  dt-bindings: clk: mstar msc313 mpll binding header

* clk-qcom: (42 commits)
  clk: qcom: Add Global Clock controller (GCC) driver for SC7280
  dt-bindings: clock: Add SC7280 GCC clock binding
  clk: qcom: rpmh: Add support for RPMH clocks on SC7280
  dt-bindings: clock: Add RPMHCC bindings for SC7280
  clk: qcom: gcc-sm8350: add gdsc
  dt-bindings: clock: Add QCOM SDM630 and SDM660 graphics clock bindings
  clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driver
  clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d
  clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers
  dt-bindings: clock: Add support for the SDM630 and SDM660 mmcc
  clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver
  clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as critical
  clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as critical
  clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting
  clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc
  clk: qcom: gdsc: Implement NO_RET_PERIPH flag
  clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on
  clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clks
  clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs
  clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as critical
  ...

* clk-warnings: (27 commits)
  clk: zynq: clkc: Remove various instances of an unused variable 'clk'
  clk: versatile: clk-icst: Fix worthy struct documentation block
  clk: ti: gate: Fix possible doc-rot in 'omap36xx_gate_clk_enable_with_hsdiv_restore'
  clk: ti: dpll: Fix misnaming of '_register_dpll()'s 'user' parameter
  clk: ti: clockdomain: Fix description for 'omap2_init_clk_clkdm's hw param
  clk: st: clkgen-fsyn: Fix worthy struct documentation demote partially filled one
  clk: st: clkgen-pll: Demote unpopulated kernel-doc header
  clk: mvebu: ap-cpu-clk: Demote non-conformant kernel-doc header
  clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc'
  clk: socfpga: clk-pll: Remove unused variable 'rc'
  clk: sifive: fu540-prci: Declare static const variable 'prci_clk_fu540' where it's used
  clk: bcm: clk-iproc-pll: Demote kernel-doc abuse
  clk: zynqmp: divider: Add missing description for 'max_div'
  clk: spear: Move prototype to accessible header
  clk: qcom: clk-rpm: Remove a bunch of superfluous code
  clk: clk-xgene: Add description for 'mask' and fix formatting for 'flags'
  clk: qcom: mmcc-msm8974: Remove unused static const tables 'mmcc_xo_mmpll0_1_2_gpll0{map}'
  clk: clk-npcm7xx: Remove unused static const tables 'npcm7xx_gates' and 'npcm7xx_divs_fx'
  clk: clk-fixed-mmio: Demote obvious kernel-doc abuse
  clk: qcom: gcc-ipq4019: Remove unused variable 'ret'
  ...
parents 11f83102 a0f9819c d90afa62 a3cc0921 bf2244ba

Documentation/devicetree/bindings/clock/intel,easic-n5x.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/intel,easic-n5x.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel SoCFPGA eASIC N5X platform clock controller binding



maintainers:

  - Dinh Nguyen <dinguyen@kernel.org>



description:

  The Intel eASIC N5X Clock controller is an integrated clock controller, which

  generates and supplies to all modules.



properties:

  compatible:

    const: intel,easic-n5x-clkmgr



  '#clock-cells':

    const: 1



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  # Clock controller node:

  - |

    clkmgr: clock-controller@ffd10000 {

      compatible = "intel,easic-n5x-clkmgr";

      reg = <0xffd10000 0x1000>;

      clocks = <&osc1>;

      #clock-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MStar/Sigmastar MSC313 MPLL



maintainers:

  - Daniel Palmer <daniel@thingy.jp>



description: |

  The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that

  takes the external xtal input and multiplies it to create a high

  frequency clock and divides that down into a number of clocks that

  peripherals use.



properties:

  compatible:

    const: mstar,msc313-mpll



  "#clock-cells":

    const: 1



  clocks:

    maxItems: 1



  reg:

    maxItems: 1



required:

  - compatible

  - "#clock-cells"

  - clocks

  - reg



additionalProperties: false



examples:

  - |

    mpll@206000 {

        compatible = "mstar,msc313-mpll";

        reg = <0x206000 0x200>;

        #clock-cells = <1>;

        clocks = <&xtal>;

    };

Documentation/devicetree/bindings/clock/qcom,a7pll.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,a7pll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm A7 PLL Binding



maintainers:

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



description:

  The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high

  frequency clock to the CPU.



properties:

  compatible:

    enum:

      - qcom,sdx55-a7pll



  reg:

    maxItems: 1



  '#clock-cells':

    const: 0



  clocks:

    items:

      - description: board XO clock



  clock-names:

    items:

      - const: bi_tcxo



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    a7pll: clock@17808000 {

        compatible = "qcom,sdx55-a7pll";

        reg = <0x17808000 0x1000>;

        clocks = <&rpmhcc RPMH_CXO_CLK>;

        clock-names = "bi_tcxo";

        #clock-cells = <0>;

    };

Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller Binding for SC7280



maintainers:

  - Taniya Das <tdas@codeaurora.org>



description: |

  Qualcomm global clock control module which supports the clocks, resets and

  power domains on SC7280.



  See also:

  - dt-bindings/clock/qcom,gcc-sc7280.h



properties:

  compatible:

    const: qcom,gcc-sc7280



  clocks:

    items:

      - description: Board XO source

      - description: Board active XO source

      - description: Sleep clock source

      - description: PCIE-0 pipe clock source

      - description: PCIE-1 pipe clock source

      - description: USF phy rx symbol 0 clock source

      - description: USF phy rx symbol 1 clock source

      - description: USF phy tx symbol 0 clock source

      - description: USB30 phy wrapper pipe clock source



  clock-names:

    items:

      - const: bi_tcxo

      - const: bi_tcxo_ao

      - const: sleep_clk

      - const: pcie_0_pipe_clk

      - const: pcie_1_pipe_clk

      - const: ufs_phy_rx_symbol_0_clk

      - const: ufs_phy_rx_symbol_1_clk

      - const: ufs_phy_tx_symbol_0_clk

      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - clocks

  - clock-names

  - reg

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,gcc-sc7280";

      reg = <0x00100000 0x1f0000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&rpmhcc RPMH_CXO_CLK_A>,

               <&sleep_clk>,

               <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,

               <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,

               <&ufs_phy_tx_symbol_0_clk>,

               <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;



      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk",

                     "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",

                     "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",

                     "usb3_phy_wrapper_gcc_usb30_pipe_clk";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8180x.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller Binding for SC8180x



maintainers:

  - Bjorn Andersson <bjorn.andersson@linaro.org>



description: |

  Qualcomm global clock control module which supports the clocks, resets and

  power domains on SC8180x.



  See also:

  - dt-bindings/clock/qcom,gcc-sc8180x.h



properties:

  compatible:

    const: qcom,gcc-sc8180x



  clocks:

    items:

      - description: Board XO source

      - description: Board active XO source

      - description: Sleep clock source



  clock-names:

    items:

      - const: bi_tcxo

      - const: bi_tcxo_ao

      - const: sleep_clk



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



  protected-clocks:

    description:

      Protected clock specifier list as per common clock binding.



required:

  - compatible

  - clocks

  - clock-names

  - reg

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,gcc-sc8180x";

      reg = <0x00100000 0x1f0000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&rpmhcc RPMH_CXO_CLK_A>,

               <&sleep_clk>;

      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...