Commit 11f83102 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-vc5', 'clk-silabs', 'clk-aspeed', 'clk-qoriq' and 'clk-rohm' into clk-next 

 - Support crystal load capacitance for Versaclock VC5
 - Add a "skip recall" DT binding for Silicon Labs' si570 to avoid glitches at boot

* clk-vc5:
  clk: vc5: Add support for optional load capacitance
  dt-bindings: clk: versaclock5: Add optional load capacitance property

* clk-silabs:
  clk: si570: Skip NVM to RAM recall operation if an optional property is set
  dt-bindings: clock: si570: Add 'silabs,skip-recall' property

* clk-aspeed:
  clk: aspeed: Fix APLL calculate formula from ast2600-A2

* clk-qoriq:
  clk: qoriq: use macros to generate pll_mask

* clk-rohm:
  clk: BD718x7: Do not depend on parent driver data
parents 242d8cf6 f3d661d6 d9d4944d 6286ce1e fa4dd53e ddddfafd

Documentation/devicetree/bindings/clock/idt,versaclock5.yaml

+6 −0
Original line number Diff line number Diff line
@@ -59,6 +59,12 @@ properties: 
    minItems: 1

    maxItems: 2



  idt,xtal-load-femtofarads:

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 9000

    maximum: 22760

    description: Optional load capacitor for XTAL1 and XTAL2



patternProperties:

  "^OUT[1-4]$":

    type: object

Documentation/devicetree/bindings/clock/silabs,si570.txt

+2 −0
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ Optional properties: 
 - clock-frequency: Output frequency to generate. This defines the output

		    frequency set during boot. It can be reprogrammed during

		    runtime through the common clock framework.

 - silabs,skip-recall: Do not perform NVM->RAM recall operation. It will rely

		       on hardware loading of RAM from NVM at power on.



Example:

	si570: clock-generator@5d {

drivers/clk/clk-ast2600.c

+27 −10
Original line number Diff line number Diff line
@@ -17,7 +17,8 @@ 


#define ASPEED_G6_NUM_CLKS		71



#define ASPEED_G6_SILICON_REV		0x004

#define ASPEED_G6_SILICON_REV		0x014

#define CHIP_REVISION_ID			GENMASK(23, 16)



#define ASPEED_G6_RESET_CTRL		0x040

#define ASPEED_G6_RESET_CTRL2		0x050
@@ -190,7 +191,22 @@ static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) 
static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)

{

	unsigned int mult, div;

	u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV);



	if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) {

		if (val & BIT(24)) {

			/* Pass through mode */

			mult = div = 1;

		} else {

			/* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */

			u32 m = val & 0x1fff;

			u32 n = (val >> 13) & 0x3f;

			u32 p = (val >> 19) & 0xf;



			mult = (m + 1);

			div = (n + 1) * (p + 1);

		}

	} else {

		if (val & BIT(20)) {

			/* Pass through mode */

			mult = div = 1;
@@ -203,6 +219,7 @@ static struct clk_hw *ast2600_calc_apll(const char *name, u32 val) 
			mult = (2 - od) * (m + 2);

			div = n + 1;

		}

	}

	return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,

			mult, div);

};

drivers/clk/clk-bd718x7.c

+7 −5
Original line number Diff line number Diff line
@@ -31,12 +31,12 @@ struct bd718xx_clk { 
	u8 reg;

	u8 mask;

	struct platform_device *pdev;

	struct rohm_regmap_dev *mfd;

	struct regmap *regmap;

};



static int bd71837_clk_set(struct bd718xx_clk *c, unsigned int status)

{

	return regmap_update_bits(c->mfd->regmap, c->reg, c->mask, status);

	return regmap_update_bits(c->regmap, c->reg, c->mask, status);

}



static void bd71837_clk_disable(struct clk_hw *hw)
@@ -62,7 +62,7 @@ static int bd71837_clk_is_enabled(struct clk_hw *hw) 
	int rval;

	struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw);



	rval = regmap_read(c->mfd->regmap, c->reg, &enabled);

	rval = regmap_read(c->regmap, c->reg, &enabled);



	if (rval)

		return rval;
@@ -82,7 +82,6 @@ static int bd71837_clk_probe(struct platform_device *pdev) 
	int rval = -ENOMEM;

	const char *parent_clk;

	struct device *parent = pdev->dev.parent;

	struct rohm_regmap_dev *mfd = dev_get_drvdata(parent);

	struct clk_init_data init = {

		.name = "bd718xx-32k-out",

		.ops = &bd71837_clk_ops,
@@ -93,6 +92,10 @@ static int bd71837_clk_probe(struct platform_device *pdev) 
	if (!c)

		return -ENOMEM;



	c->regmap = dev_get_regmap(pdev->dev.parent, NULL);

	if (!c->regmap)

		return -ENODEV;



	init.num_parents = 1;

	parent_clk = of_clk_get_parent_name(parent->of_node, 0);
@@ -119,7 +122,6 @@ static int bd71837_clk_probe(struct platform_device *pdev) 
		dev_err(&pdev->dev, "Unknown clk chip\n");

		return -EINVAL;

	}

	c->mfd = mfd;

	c->pdev = pdev;

	c->hw.init = &init;

drivers/clk/clk-qoriq.c

+43 −19
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright 2013 Freescale Semiconductor, Inc.

 * Copyright 2021 NXP

 *

 * clock driver for Freescale QorIQ SoCs.

 */
@@ -564,7 +565,9 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, 1, 1, 1, -1

		},

		.pll_mask = 0x3f,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |

			    BIT(CGB_PLL1) | BIT(CGB_PLL2),

		.flags = CG_PLL_8BIT,

	},

	{
@@ -580,7 +583,9 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, 1, 1, 1, -1

		},

		.pll_mask = 0x3f,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |

			    BIT(CGB_PLL1) | BIT(CGB_PLL2),

		.flags = CG_PLL_8BIT,

	},

	{
@@ -591,7 +596,8 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, -1

		},

		.pll_mask = 0x03,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2),

	},

	{

		.compat = "fsl,ls1028a-clockgen",
@@ -605,7 +611,8 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, 0, 0, 0, -1

		},

		.pll_mask = 0x07,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2),

		.flags = CG_VER3 | CG_LITTLE_ENDIAN,

	},

	{
@@ -620,7 +627,8 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, -1

		},

		.pll_mask = 0x07,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2),

		.flags = CG_PLL_8BIT,

	},

	{
@@ -635,7 +643,8 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, -1

		},

		.pll_mask = 0x07,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2),

		.flags = CG_PLL_8BIT,

	},

	{
@@ -649,7 +658,8 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, 0, -1

		},

		.pll_mask = 0x07,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2),

		.flags = CG_VER3 | CG_LITTLE_ENDIAN,

	},

	{
@@ -660,7 +670,7 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, -1

		},

		.pll_mask = 0x03,

		.pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),

	},

	{

		.compat = "fsl,ls2080a-clockgen",
@@ -670,7 +680,9 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, 0, 1, 1, -1

		},

		.pll_mask = 0x37,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2) |

			    BIT(CGB_PLL1) | BIT(CGB_PLL2),

		.flags = CG_VER3 | CG_LITTLE_ENDIAN,

	},

	{
@@ -681,7 +693,9 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, 0, 0, 0, 1, 1, 1, 1, -1

		},

		.pll_mask = 0x37,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2) |

			    BIT(CGB_PLL1) | BIT(CGB_PLL2),

		.flags = CG_VER3 | CG_LITTLE_ENDIAN,

	},

	{
@@ -694,7 +708,8 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, 0, 1, 1, -1

		},

		.pll_mask = 0x07,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2),

	},

	{

		.compat = "fsl,p3041-clockgen",
@@ -706,7 +721,8 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, 0, 1, 1, -1

		},

		.pll_mask = 0x07,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2),

	},

	{

		.compat = "fsl,p4080-clockgen",
@@ -718,7 +734,9 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, 0, 0, 0, 1, 1, 1, 1, -1

		},

		.pll_mask = 0x1f,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2) |

			    BIT(CGA_PLL3) | BIT(CGA_PLL4),

	},

	{

		.compat = "fsl,p5020-clockgen",
@@ -730,7 +748,8 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, 1, -1

		},

		.pll_mask = 0x07,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2),

	},

	{

		.compat = "fsl,p5040-clockgen",
@@ -742,7 +761,8 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, 0, 1, 1, -1

		},

		.pll_mask = 0x0f,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3),

	},

	{

		.compat = "fsl,t1023-clockgen",
@@ -757,7 +777,7 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, 0, -1

		},

		.pll_mask = 0x03,

		.pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),

		.flags = CG_PLL_8BIT,

	},

	{
@@ -770,7 +790,8 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, 0, 0, 0, -1

		},

		.pll_mask = 0x07,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2),

		.flags = CG_PLL_8BIT,

	},

	{
@@ -786,7 +807,8 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, -1

		},

		.pll_mask = 0x07,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2),

		.flags = CG_PLL_8BIT,

	},

	{
@@ -802,7 +824,9 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.cmux_to_group = {

			0, 0, 1, -1

		},

		.pll_mask = 0x3f,

		.pll_mask = BIT(PLATFORM_PLL) |

			    BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |

			    BIT(CGB_PLL1) | BIT(CGB_PLL2),

		.flags = CG_PLL_8BIT,

	},

	{},