Commit 6286ce1e authored by Ryan Chen's avatar Ryan Chen Committed by Stephen Boyd
Browse files

clk: aspeed: Fix APLL calculate formula from ast2600-A2 



Starting from A2, the A-PLL calculation has changed. Use the
existing formula for A0/A1 and the new formula for A2 onwards.

Fixes: d3d04f6c ("clk: Add support for AST2600 SoC")
Signed-off-by: default avatarRyan Chen <ryan_chen@aspeedtech.com>
Link: https://lore.kernel.org/r/20210119061715.6043-1-ryan_chen@aspeedtech.com


Reviewed-by: default avatarJoel Stanley <joel@jms.id.au>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 5c8fe583

drivers/clk/clk-ast2600.c

+27 −10
Original line number Diff line number Diff line
@@ -17,7 +17,8 @@ 


#define ASPEED_G6_NUM_CLKS		71



#define ASPEED_G6_SILICON_REV		0x004

#define ASPEED_G6_SILICON_REV		0x014

#define CHIP_REVISION_ID			GENMASK(23, 16)



#define ASPEED_G6_RESET_CTRL		0x040

#define ASPEED_G6_RESET_CTRL2		0x050
@@ -190,7 +191,22 @@ static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) 
static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)

{

	unsigned int mult, div;

	u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV);



	if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) {

		if (val & BIT(24)) {

			/* Pass through mode */

			mult = div = 1;

		} else {

			/* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */

			u32 m = val & 0x1fff;

			u32 n = (val >> 13) & 0x3f;

			u32 p = (val >> 19) & 0xf;



			mult = (m + 1);

			div = (n + 1) * (p + 1);

		}

	} else {

		if (val & BIT(20)) {

			/* Pass through mode */

			mult = div = 1;
@@ -203,6 +219,7 @@ static struct clk_hw *ast2600_calc_apll(const char *name, u32 val) 
			mult = (2 - od) * (m + 2);

			div = n + 1;

		}

	}

	return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,

			mult, div);

};