Commit 4caab28a authored by Kunihiko Hayashi's avatar Kunihiko Hayashi Committed by Lorenzo Pieralisi
Browse files

PCI: uniphier: Serialize INTx masking/unmasking and fix the bit operation 



The condition register PCI_RCV_INTX is used in irq_mask() and irq_unmask()
callbacks. Accesses to register can occur at the same time without a lock.
Add a lock into each callback to prevent the issue.

And INTX mask and unmask fields in PCL_RCV_INTX register should only be
set/reset for each bit. Clearing by PCL_RCV_INTX_ALL_MASK should be
removed.

INTX status fields in PCL_RCV_INTX register only indicates each INTX
interrupt status, so the handler can't clear by writing 1 to the field.
The status is expected to be cleared by the interrupt origin.
The ack function has no meaning, so should remove it.

Suggested-by: default avatarPali Rohár <pali@kernel.org>
Link: https://lore.kernel.org/r/1631924579-24567-1-git-send-email-hayashi.kunihiko@socionext.com


Fixes: 7e6d5cd8 ("PCI: uniphier: Add UniPhier PCIe host controller support")
Signed-off-by: default avatarKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: default avatarPali Rohár <pali@kernel.org>
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
parent 7e919677

drivers/pci/controller/dwc/pcie-uniphier.c

+10 −16
Original line number Diff line number Diff line
@@ -168,30 +168,21 @@ static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv) 
	writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX);

}



static void uniphier_pcie_irq_ack(struct irq_data *d)

{

	struct pcie_port *pp = irq_data_get_irq_chip_data(d);

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);

	u32 val;



	val = readl(priv->base + PCL_RCV_INTX);

	val &= ~PCL_RCV_INTX_ALL_STATUS;

	val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_STATUS_SHIFT);

	writel(val, priv->base + PCL_RCV_INTX);

}



static void uniphier_pcie_irq_mask(struct irq_data *d)

{

	struct pcie_port *pp = irq_data_get_irq_chip_data(d);

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);

	unsigned long flags;

	u32 val;



	raw_spin_lock_irqsave(&pp->lock, flags);



	val = readl(priv->base + PCL_RCV_INTX);

	val &= ~PCL_RCV_INTX_ALL_MASK;

	val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);

	writel(val, priv->base + PCL_RCV_INTX);



	raw_spin_unlock_irqrestore(&pp->lock, flags);

}



static void uniphier_pcie_irq_unmask(struct irq_data *d)
@@ -199,17 +190,20 @@ static void uniphier_pcie_irq_unmask(struct irq_data *d) 
	struct pcie_port *pp = irq_data_get_irq_chip_data(d);

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);

	unsigned long flags;

	u32 val;



	raw_spin_lock_irqsave(&pp->lock, flags);



	val = readl(priv->base + PCL_RCV_INTX);

	val &= ~PCL_RCV_INTX_ALL_MASK;

	val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);

	writel(val, priv->base + PCL_RCV_INTX);



	raw_spin_unlock_irqrestore(&pp->lock, flags);

}



static struct irq_chip uniphier_pcie_irq_chip = {

	.name = "PCI",

	.irq_ack = uniphier_pcie_irq_ack,

	.irq_mask = uniphier_pcie_irq_mask,

	.irq_unmask = uniphier_pcie_irq_unmask,

};