Commit 4b569ded authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/acr/ga102: initial support 



v2. fixup for ga103 early merge

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Signed-off-by: default avatarGourav Samaiya <gsamaiya@nvidia.com>
parent a51c69ee

drivers/gpu/drm/nouveau/include/nvfw/acr.h

+85 −0
Original line number Diff line number Diff line
@@ -39,6 +39,23 @@ struct wpr_header_v1 { 


void wpr_header_v1_dump(struct nvkm_subdev *, const struct wpr_header_v1 *);



struct wpr_generic_header {

#define WPR_GENERIC_HEADER_ID_LSF_UCODE_DESC     1

#define WPR_GENERIC_HEADER_ID_LSF_WPR_HEADER     2

#define WPR_GENERIC_HEADER_ID_LSF_SHARED_SUB_WPR 3

#define WPR_GENERIC_HEADER_ID_LSF_LSB_HEADER     4

	u16 identifier;

	u16 version;

	u32 size;

};



struct wpr_header_v2 {

	struct wpr_generic_header hdr;

	struct wpr_header_v1 wpr;

};



void wpr_header_v2_dump(struct nvkm_subdev *, const struct wpr_header_v2 *);



struct lsf_signature {

	u8 prd_keys[2][16];

	u8 dbg_keys[2][16];
@@ -89,6 +106,74 @@ struct lsb_header_v1 { 


void lsb_header_v1_dump(struct nvkm_subdev *, struct lsb_header_v1 *);



struct lsb_header_v2 {

	struct wpr_generic_header hdr;

	struct lsf_signature_v2 {

		struct wpr_generic_header hdr;

		u32 falcon_id;

		u8 prd_present;

		u8 dbg_present;

		u16 reserved;

		u32 sig_size;

		u8 prod_sig[2][384 + 128];

		u8 debug_sig[2][384 + 128];

		u16 sig_algo_ver;

		u16 sig_algo;

		u16 hash_algo_ver;

		u16 hash_algo;

		u32 sig_algo_padding_type;

		u8 depmap[11 * 2 * 4];

		u32 depmap_count;

		u8 supports_versioning;

		u8 pad[3];

		u32 ls_ucode_version;

		u32 ls_ucode_id;

		u32 ucode_ls_encrypted;

		u32 ls_eng_algo_type;

		u32 ls_eng_algo_ver;

		u8 ls_enc_iv[16];

		u8 rsvd[36];

	} signature;

	u32 ucode_off;

	u32 ucode_size;

	u32 data_size;

	u32 bl_code_size;

	u32 bl_imem_off;

	u32 bl_data_off;

	u32 bl_data_size;

	u32 rsvd0;

	u32 app_code_off;

	u32 app_code_size;

	u32 app_data_off;

	u32 app_data_size;

	u32 app_imem_offset;

	u32 app_dmem_offset;

	u32 flags;

	u32 monitor_code_offset;

	u32 monitor_data_offset;

	u32 manifest_offset;

	struct hs_fmc_params {

		u8 hs_fmc;

		u8 padding[3];

		u16 pkc_algo;

		u16 pkc_algo_version;

		u32 engid_mask;

		u32 ucode_id;

		u32 fuse_ver;

		u8 pkc_signature[384 + 128];

		u8 pkc_key[2048];

		u8 rsvd[4];

	} hs_fmc_params;

	struct hs_ovl_sig_blob_params {

		u8 hs_ovl_sig_blob_present;

		u32 hs_ovl_sig_blob_offset;

		u32 hs_ovl_sig_blob_size;

	} hs_ovl_sig_blob_params;

	u8 rsvd[20];

};



void lsb_header_v2_dump(struct nvkm_subdev *, struct lsb_header_v2 *);



struct flcn_acr_desc {

	union {

		u8 reserved_dmem[0x200];

drivers/gpu/drm/nouveau/include/nvfw/ls.h

+51 −0
Original line number Diff line number Diff line
@@ -50,4 +50,55 @@ struct nvfw_ls_desc_v1 { 


const struct nvfw_ls_desc_v1 *

nvfw_ls_desc_v1(struct nvkm_subdev *, const void *);



struct nvfw_ls_desc_v2 {

	u32 descriptor_size;

	u32 image_size;

	u32 tools_version;

	u32 app_version;

	char date[64];

	u32 secure_bootloader;

	u32 bootloader_start_offset;

	u32 bootloader_size;

	u32 bootloader_imem_offset;

	u32 bootloader_entry_point;

	u32 app_start_offset;

	u32 app_size;

	u32 app_imem_offset;

	u32 app_imem_entry;

	u32 app_dmem_offset;

	u32 app_resident_code_offset;

	u32 app_resident_code_size;

	u32 app_resident_data_offset;

	u32 app_resident_data_size;

	u32 nb_imem_overlays;

	u32 nb_dmem_overlays;

	struct {

		u32 start;

		u32 size;

	} load_ovl[64];

};



const struct nvfw_ls_desc_v2 *nvfw_ls_desc_v2(struct nvkm_subdev *, const void *);



struct nvfw_ls_hsbl_bin_hdr {

	u32 bin_magic;

	u32 bin_ver;

	u32 bin_size;

	u32 header_offset;

};



const struct nvfw_ls_hsbl_bin_hdr *nvfw_ls_hsbl_bin_hdr(struct nvkm_subdev *, const void *);



struct nvfw_ls_hsbl_hdr {

	u32 sig_prod_offset;

	u32 sig_prod_size;

	u32 patch_loc;

	u32 patch_sig;

	u32 meta_data_offset;

	u32 meta_data_size;

	u32 num_sig;

};



const struct nvfw_ls_hsbl_hdr *nvfw_ls_hsbl_hdr(struct nvkm_subdev *, const void *);

#endif

drivers/gpu/drm/nouveau/include/nvfw/sec2.h

+40 −0
Original line number Diff line number Diff line
@@ -34,6 +34,29 @@ struct nv_sec2_init_msg { 
	u16 sw_managed_area_size;

};



struct nv_sec2_init_msg_v1 {

	struct nvfw_falcon_msg hdr;

#define NV_SEC2_INIT_MSG_INIT                                              0x00

	u8 msg_type;



	u8 num_queues;

	u16 os_debug_entry_point;



	struct {

		u32 offset;

		u16 size;

		u8 index;

#define NV_SEC2_INIT_MSG_QUEUE_ID_CMDQ                                     0x00

#define NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ                                     0x01

		u8 id;

	} queue_info[2];



	u32 sw_managed_area_offset;

	u16 sw_managed_area_size;



	u32 unkn[8];

};



struct nv_sec2_acr_cmd {

	struct nvfw_falcon_cmd hdr;

#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON                                   0x00
@@ -62,4 +85,21 @@ struct nv_sec2_acr_bootstrap_falcon_msg { 
#define NV_SEC2_UNIT_V2_INIT   0x01

#define NV_SEC2_UNIT_V2_UNLOAD 0x05

#define NV_SEC2_UNIT_V2_ACR    0x07



struct nv_sec2_acr_bootstrap_falcon_cmd_v1 {

	struct nv_sec2_acr_cmd cmd;

#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES                 0x00000000

#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO                  0x00000001

	u32 flags;

	u32 falcon_id;

	u32 unkn08;

	u32 unkn0c;

};



struct nv_sec2_acr_bootstrap_falcon_msg_v1 {

	struct nv_sec2_acr_msg msg;

	u32 error_code;

	u32 falcon_id;

	u32 unkn08;

};

#endif

drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h

+1 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ void gm200_flcn_tracepc(struct nvkm_falcon *); 
int gp102_flcn_reset_eng(struct nvkm_falcon *);

extern const struct nvkm_falcon_func_pio gp102_flcn_emem_pio;



int ga102_flcn_select(struct nvkm_falcon *);

int ga102_flcn_reset_prep(struct nvkm_falcon *);

int ga102_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *);

extern const struct nvkm_falcon_func_dma ga102_flcn_dma;

drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h

+1 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ int nvkm_falcon_new_(const struct nvkm_falcon_func *, struct nvkm_device *, 
struct nvkm_falcon_func {

	int (*disable)(struct nvkm_falcon *);

	int (*enable)(struct nvkm_falcon *);

	int (*select)(struct nvkm_falcon *);

	u32 addr2;

	bool reset_pmc;

	int (*reset_eng)(struct nvkm_falcon *);