Commit a51c69ee authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/fb/ga102: load and boot VPR scrubber FW 



v2. fixup for ga103 early merge

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Signed-off-by: default avatarGourav Samaiya <gsamaiya@nvidia.com>
parent 21876b0e

drivers/gpu/drm/nouveau/include/nvfw/hs.h

+28 −0
Original line number Diff line number Diff line
@@ -17,6 +17,20 @@ struct nvfw_hs_header { 


const struct nvfw_hs_header *nvfw_hs_header(struct nvkm_subdev *, const void *);



struct nvfw_hs_header_v2 {

	u32 sig_prod_offset;

	u32 sig_prod_size;

	u32 patch_loc;

	u32 patch_sig;

	u32 meta_data_offset;

	u32 meta_data_size;

	u32 num_sig;

	u32 header_offset;

	u32 header_size;

};



const struct nvfw_hs_header_v2 *nvfw_hs_header_v2(struct nvkm_subdev *, const void *);



struct nvfw_hs_load_header {

	u32 non_sec_code_off;

	u32 non_sec_code_size;
@@ -28,4 +42,18 @@ struct nvfw_hs_load_header { 


const struct nvfw_hs_load_header *

nvfw_hs_load_header(struct nvkm_subdev *, const void *);



struct nvfw_hs_load_header_v2 {

	u32 os_code_offset;

	u32 os_code_size;

	u32 os_data_offset;

	u32 os_data_size;

	u32 num_apps;

	struct {

		u32 offset;

		u32 size;

	} app[0];

};



const struct nvfw_hs_load_header_v2 *nvfw_hs_load_header_v2(struct nvkm_subdev *, const void *);

#endif

drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h

+25 −0
Original line number Diff line number Diff line
@@ -31,6 +31,13 @@ struct nvkm_falcon_func_pio { 
	void (*rd)(struct nvkm_falcon *, u8 port, const u8 *img, int len);

};



struct nvkm_falcon_func_dma {

	int (*init)(struct nvkm_falcon *, u64 dma_addr, int xfer_len,

		    enum nvkm_falcon_mem, bool sec, u32 *cmd);

	void (*xfer)(struct nvkm_falcon *, u32 mem_base, u32 dma_base, u32 cmd);

	bool (*done)(struct nvkm_falcon *);

};



int nvkm_falcon_ctor(const struct nvkm_falcon_func *, struct nvkm_subdev *owner,

		     const char *name, u32 addr, struct nvkm_falcon *);

void nvkm_falcon_dtor(struct nvkm_falcon *);
@@ -39,6 +46,8 @@ int nvkm_falcon_pio_wr(struct nvkm_falcon *, const u8 *img, u32 img_base, u8 por 
		       enum nvkm_falcon_mem mem_type, u32 mem_base, int len, u16 tag, bool sec);

int nvkm_falcon_pio_rd(struct nvkm_falcon *, u8 port, enum nvkm_falcon_mem type, u32 mem_base,

		       const u8 *img, u32 img_base, int len);

int nvkm_falcon_dma_wr(struct nvkm_falcon *, const u8 *img, u64 dma_addr, u32 dma_base,

		       enum nvkm_falcon_mem mem_type, u32 mem_base, int len, bool sec);



int gm200_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *);

int gm200_flcn_disable(struct nvkm_falcon *);
@@ -52,6 +61,10 @@ void gm200_flcn_tracepc(struct nvkm_falcon *); 
int gp102_flcn_reset_eng(struct nvkm_falcon *);

extern const struct nvkm_falcon_func_pio gp102_flcn_emem_pio;



int ga102_flcn_reset_prep(struct nvkm_falcon *);

int ga102_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *);

extern const struct nvkm_falcon_func_dma ga102_flcn_dma;



void nvkm_falcon_v1_load_imem(struct nvkm_falcon *,

			      void *, u32, u32, u16, u8, bool);

void nvkm_falcon_v1_load_dmem(struct nvkm_falcon *, void *, u32, u32, u8);
@@ -87,6 +100,9 @@ struct nvkm_falcon_fw { 
	u32 sig_size;

	int sig_nr;

	u8 *sigs;

	u32 fuse_ver;

	u32 engine_id;

	u32 ucode_id;



	u32 nmem_base_img;

	u32 nmem_base;
@@ -117,6 +133,9 @@ int nvkm_falcon_fw_ctor(const struct nvkm_falcon_fw_func *, const char *name, st 
int nvkm_falcon_fw_ctor_hs(const struct nvkm_falcon_fw_func *, const char *name,

			   struct nvkm_subdev *, const char *bl, const char *img, int ver,

			   struct nvkm_falcon *falcon, struct nvkm_falcon_fw *fw);

int nvkm_falcon_fw_ctor_hs_v2(const struct nvkm_falcon_fw_func *, const char *name,

			      struct nvkm_subdev *, const char *img, int ver, struct nvkm_falcon *,

			      struct nvkm_falcon_fw *);

int nvkm_falcon_fw_sign(struct nvkm_falcon_fw *, u32 sig_base_img, u32 sig_size, const u8 *sigs,

			int sig_nr_prd, u32 sig_base_prd, int sig_nr_dbg, u32 sig_base_dbg);

int nvkm_falcon_fw_patch(struct nvkm_falcon_fw *);
@@ -132,6 +151,12 @@ int gm200_flcn_fw_reset(struct nvkm_falcon_fw *); 
int gm200_flcn_fw_load(struct nvkm_falcon_fw *);

int gm200_flcn_fw_boot(struct nvkm_falcon_fw *, u32 *, u32 *, u32, u32);



int ga100_flcn_fw_signature(struct nvkm_falcon_fw *, u32 *);



extern const struct nvkm_falcon_fw_func ga102_flcn_fw;

int ga102_flcn_fw_load(struct nvkm_falcon_fw *);

int ga102_flcn_fw_boot(struct nvkm_falcon_fw *, u32 *, u32 *, u32, u32);



#define FLCNFW_PRINTK(f,l,p,fmt,a...) FLCN_PRINTK((f)->falcon, l, p, "%s: "fmt, (f)->fw.name, ##a)

#define FLCNFW_DBG(f,fmt,a...) FLCNFW_PRINTK((f), DEBUG, info, fmt"\n", ##a)

#define FLCNFW_ERR(f,fmt,a...) FLCNFW_PRINTK((f), ERROR, err, fmt"\n", ##a)

drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h

+6 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ struct nvkm_falcon { 
	struct nvkm_subdev *owner;

	const char *name;

	u32 addr;

	u32 addr2;



	struct mutex mutex;

	struct mutex dmem_mutex;
@@ -59,8 +60,10 @@ int nvkm_falcon_new_(const struct nvkm_falcon_func *, struct nvkm_device *, 
struct nvkm_falcon_func {

	int (*disable)(struct nvkm_falcon *);

	int (*enable)(struct nvkm_falcon *);

	u32 addr2;

	bool reset_pmc;

	int (*reset_eng)(struct nvkm_falcon *);

	int (*reset_prep)(struct nvkm_falcon *);

	int (*reset_wait_mem_scrubbing)(struct nvkm_falcon *);



	u32 debug;
@@ -69,7 +72,10 @@ struct nvkm_falcon_func { 
	bool bind_intr;



	const struct nvkm_falcon_func_pio *imem_pio;

	const struct nvkm_falcon_func_dma *imem_dma;



	const struct nvkm_falcon_func_pio *dmem_pio;

	const struct nvkm_falcon_func_dma *dmem_dma;



	u32 emem_addr;

	const struct nvkm_falcon_func_pio *emem_pio;

drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h

+1 −0
Original line number Diff line number Diff line
@@ -12,4 +12,5 @@ struct nvkm_nvdec { 
};



int gm107_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);

int ga102_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);

#endif

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+5 −0
Original line number Diff line number Diff line
@@ -2615,6 +2615,7 @@ nv172_chipset = { 
	.disp     = { 0x00000001, ga102_disp_new },

	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, ga102_fifo_new },

	.nvdec    = { 0x00000001, ga102_nvdec_new },

};



static const struct nvkm_device_chip
@@ -2639,6 +2640,7 @@ nv173_chipset = { 
	.disp     = { 0x00000001, ga102_disp_new },

	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, ga102_fifo_new },

	.nvdec    = { 0x00000001, ga102_nvdec_new },

};



static const struct nvkm_device_chip
@@ -2663,6 +2665,7 @@ nv174_chipset = { 
	.disp     = { 0x00000001, ga102_disp_new },

	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, ga102_fifo_new },

	.nvdec    = { 0x00000001, ga102_nvdec_new },

};



static const struct nvkm_device_chip
@@ -2687,6 +2690,7 @@ nv176_chipset = { 
	.disp     = { 0x00000001, ga102_disp_new },

	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, ga102_fifo_new },

	.nvdec    = { 0x00000001, ga102_nvdec_new },

};



static const struct nvkm_device_chip
@@ -2711,6 +2715,7 @@ nv177_chipset = { 
	.disp     = { 0x00000001, ga102_disp_new },

	.dma      = { 0x00000001, gv100_dma_new },

	.fifo     = { 0x00000001, ga102_fifo_new },

	.nvdec    = { 0x00000001, ga102_nvdec_new },

};



struct nvkm_subdev *