Commit 4accdb98 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'timers-core-2023-09-04-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull clocksource/clockevent driver updates from Thomas Gleixner:

 - Remove the OXNAS driver instead of adding a new one!

 - A set of boring fixes, cleanups and improvements

* tag 'timers-core-2023-09-04-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  clocksource: Explicitly include correct DT includes
  clocksource/drivers/sun5i: Convert to platform device driver
  clocksource/drivers/sun5i: Remove pointless struct
  clocksource/drivers/sun5i: Remove duplication of code and data
  clocksource/drivers/loongson1: Set variable ls1x_timer_lock storage-class-specifier to static
  clocksource/drivers/arm_arch_timer: Disable timer before programming CVAL
  dt-bindings: timer: oxsemi,rps-timer: remove obsolete bindings
  clocksource/drivers/timer-oxnas-rps: Remove obsolete timer driver
parents 7a1415ee 5146e1f5

Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt

deleted100644 → 0
+0 −17
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Oxford Semiconductor OXNAS SoCs Family RPS Timer

================================================



Required properties:

- compatible: Should be "oxsemi,ox810se-rps-timer" or "oxsemi,ox820-rps-timer"

- reg : Specifies base physical address and size of the registers.

- interrupts : The interrupts of the two timers

- clocks : The phandle of the timer clock source



example:



timer0: timer@200 {

	compatible = "oxsemi,ox810se-rps-timer";

	reg = <0x200 0x40>;

	clocks = <&rpsclk>;

	interrupts = <4 5>;

};

drivers/clocksource/Kconfig

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@@ -461,13 +461,6 @@ config VF_PIT_TIMER 
	help

	  Support for Periodic Interrupt Timer on Freescale Vybrid Family SoCs.



config OXNAS_RPS_TIMER

	bool "Oxford Semiconductor OXNAS RPS Timers driver" if COMPILE_TEST

	select TIMER_OF

	select CLKSRC_MMIO

	help

	  This enables support for the Oxford Semiconductor OXNAS RPS timers.



config SYS_SUPPORTS_SH_CMT

	bool

drivers/clocksource/Makefile

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@@ -54,7 +54,6 @@ obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o 
obj-$(CONFIG_MTK_CPUX_TIMER)	+= timer-mediatek-cpux.o

obj-$(CONFIG_CLKSRC_PISTACHIO)	+= timer-pistachio.o

obj-$(CONFIG_CLKSRC_TI_32K)	+= timer-ti-32k.o

obj-$(CONFIG_OXNAS_RPS_TIMER)	+= timer-oxnas-rps.o

obj-$(CONFIG_OWL_TIMER)		+= timer-owl.o

obj-$(CONFIG_MILBEAUT_TIMER)	+= timer-milbeaut.o

obj-$(CONFIG_SPRD_TIMER)	+= timer-sprd.o

drivers/clocksource/arm_arch_timer.c

+7 −0
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@@ -792,6 +792,13 @@ static __always_inline void set_next_event_mem(const int access, unsigned long e 
	u64 cnt;



	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);



	/* Timer must be disabled before programming CVAL */

	if (ctrl & ARCH_TIMER_CTRL_ENABLE) {

		ctrl &= ~ARCH_TIMER_CTRL_ENABLE;

		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);

	}



	ctrl |= ARCH_TIMER_CTRL_ENABLE;

	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;

drivers/clocksource/timer-loongson1-pwm.c

+1 −1
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@@ -28,7 +28,7 @@ 


#define CNTR_WIDTH		24



DEFINE_RAW_SPINLOCK(ls1x_timer_lock);

static DEFINE_RAW_SPINLOCK(ls1x_timer_lock);



struct ls1x_clocksource {

	void __iomem *reg_base;