Commit 5146e1f5 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'timers-v6.6-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core 

Pull clocksource/clockdevice updates from Daniel Lezcano:

  - Remove oxnas the 0x810 and the 0x820 timer drivers, the platform
    being no longer maintained and removed (Neil Armstrong)

  - Disable the timer before programming the CVAL as there is no
    guarantee of atomicity on the ARM architected timer (Walter Chang)

  - Set variable ls1x_timer_lock static on the Loongson1 (Tom Rix)

  - Remove duplication of code and data by factoring out the structures
    into a single one and convert to the platform driver on the sun5i
    (Mans Rullgard)

  - Explicitly include correct DT includes (Rob Herring)
parents d2b32be7 0a8b07c7

Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt

deleted100644 → 0
+0 −17
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Oxford Semiconductor OXNAS SoCs Family RPS Timer

================================================



Required properties:

- compatible: Should be "oxsemi,ox810se-rps-timer" or "oxsemi,ox820-rps-timer"

- reg : Specifies base physical address and size of the registers.

- interrupts : The interrupts of the two timers

- clocks : The phandle of the timer clock source



example:



timer0: timer@200 {

	compatible = "oxsemi,ox810se-rps-timer";

	reg = <0x200 0x40>;

	clocks = <&rpsclk>;

	interrupts = <4 5>;

};

drivers/clocksource/Kconfig

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@@ -461,13 +461,6 @@ config VF_PIT_TIMER 
	help

	  Support for Periodic Interrupt Timer on Freescale Vybrid Family SoCs.



config OXNAS_RPS_TIMER

	bool "Oxford Semiconductor OXNAS RPS Timers driver" if COMPILE_TEST

	select TIMER_OF

	select CLKSRC_MMIO

	help

	  This enables support for the Oxford Semiconductor OXNAS RPS timers.



config SYS_SUPPORTS_SH_CMT

	bool

drivers/clocksource/Makefile

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@@ -54,7 +54,6 @@ obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o 
obj-$(CONFIG_MTK_CPUX_TIMER)	+= timer-mediatek-cpux.o

obj-$(CONFIG_CLKSRC_PISTACHIO)	+= timer-pistachio.o

obj-$(CONFIG_CLKSRC_TI_32K)	+= timer-ti-32k.o

obj-$(CONFIG_OXNAS_RPS_TIMER)	+= timer-oxnas-rps.o

obj-$(CONFIG_OWL_TIMER)		+= timer-owl.o

obj-$(CONFIG_MILBEAUT_TIMER)	+= timer-milbeaut.o

obj-$(CONFIG_SPRD_TIMER)	+= timer-sprd.o

drivers/clocksource/arm_arch_timer.c

+7 −0
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@@ -774,6 +774,13 @@ static __always_inline void set_next_event_mem(const int access, unsigned long e 
	u64 cnt;



	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);



	/* Timer must be disabled before programming CVAL */

	if (ctrl & ARCH_TIMER_CTRL_ENABLE) {

		ctrl &= ~ARCH_TIMER_CTRL_ENABLE;

		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);

	}



	ctrl |= ARCH_TIMER_CTRL_ENABLE;

	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;

drivers/clocksource/bcm2835_timer.c

+1 −1
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@@ -10,9 +10,9 @@ 
#include <linux/irqreturn.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>

#include <linux/of_platform.h>

#include <linux/slab.h>

#include <linux/string.h>

#include <linux/sched_clock.h>