Commit 49e8e634 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-6.2-2022-11-04' of https://gitlab.freedesktop.org/agd5f/linux into drm-next 



amd-drm-next-6.2-2022-11-04:

amdgpu:
- Add TMZ support for GC 11.0.1
- More IP version check conversions
- Mode2 reset fixes for sienna cichlid
- SMU 13.x fixes
- RAS enablement on MP 13.x
- Replace kmap with kmap_local_page()
- Misc Clang warning fixes
- SR-IOV fixes for GC 11.x
- PCI AER fix
- DCN 3.2.x commit sequence rework
- SDMA 4.x doorbell fix
- Expose additional new GC 11.x firmware versions
- Misc code cleanups
- S0i3 fixes
- More DC FPU cleanup
- Add more DC kerneldoc
- Misc spelling and grammer fixes
- DCN 3.1.x fixes
- Plane modifier fix
- MCA RAS enablement
- Secure display locking fix
- RAS TA rework
- RAS EEPROM fixes
- Fail suspend if eviction fails
- Drop AMD specific DSC workarounds in favor of drm EDID quirks
- SR-IOV suspend/resume fixes
- Enable DCN support for ARM
- Enable secure display on DCN 2.1

amdkfd:
- Cache size fixes for GC 10.3.x
- kfd_dev struct cleanup
- GC11.x CWSR trap handler fix
- Userptr fixes
- Warning fixes

radeon:
- Replace kmap with kmap_local_page()

UAPI:
- Expose additional new GC 11.x firmware versions via the existing INFO query

drm:
- Add some new EDID DSC quirks

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

# Conflicts:
#	drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221104205827.6008-1-alexander.deucher@amd.com
parents 60ba8c5b fcf00f8d

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+3 −1
Original line number Diff line number Diff line
@@ -219,10 +219,12 @@ extern int amdgpu_use_xgmi_p2p; 
extern int sched_policy;

extern bool debug_evictions;

extern bool no_system_mem_limit;

extern int halt_if_hws_hang;

#else

static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;

static const bool __maybe_unused debug_evictions; /* = false */

static const bool __maybe_unused no_system_mem_limit;

static const int __maybe_unused halt_if_hws_hang;

#endif

#ifdef CONFIG_HSA_AMD_P2P

extern bool pcie_p2p;
@@ -675,7 +677,7 @@ enum amd_hw_ip_block_type { 
	MAX_HWIP

};



#define HWIP_MAX_INSTANCE	11

#define HWIP_MAX_INSTANCE	28



#define HW_ID_MAX		300

#define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+9 −4
Original line number Diff line number Diff line
@@ -195,7 +195,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 
		}



		adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,

						adev_to_drm(adev), &gpu_resources);

							&gpu_resources);



		amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
@@ -706,6 +706,13 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 


void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)

{

	/* Temporary workaround to fix issues observed in some

	 * compute applications when GFXOFF is enabled on GFX11.

	 */

	if (IP_VERSION_MAJ(adev->ip_versions[GC_HWIP][0]) == 11) {

		pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled");

		amdgpu_gfx_off_ctrl(adev, idle);

	}

	amdgpu_dpm_switch_power_profile(adev,

					PP_SMC_POWER_PROFILE_COMPUTE,

					!idle);
@@ -753,9 +760,7 @@ bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) 


void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset)

{

	struct ras_err_data err_data = {0, 0, 0, NULL};



	amdgpu_umc_poison_handler(adev, &err_data, reset);

	amdgpu_umc_poison_handler(adev, reset);

}



bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h

+1 −2
Original line number Diff line number Diff line
@@ -353,7 +353,6 @@ int kgd2kfd_init(void); 
void kgd2kfd_exit(void);

struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf);

bool kgd2kfd_device_init(struct kfd_dev *kfd,

			 struct drm_device *ddev,

			 const struct kgd2kfd_shared_resources *gpu_resources);

void kgd2kfd_device_exit(struct kfd_dev *kfd);

void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
@@ -381,7 +380,7 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 
}



static inline

bool kgd2kfd_device_init(struct kfd_dev *kfd, struct drm_device *ddev,

bool kgd2kfd_device_init(struct kfd_dev *kfd,

				const struct kgd2kfd_shared_resources *gpu_resources)

{

	return false;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

+2 −2
Original line number Diff line number Diff line
@@ -787,7 +787,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid, 
	for (se_idx = 0; se_idx < se_cnt; se_idx++) {

		for (sh_idx = 0; sh_idx < sh_cnt; sh_idx++) {



			gfx_v9_0_select_se_sh(adev, se_idx, sh_idx, 0xffffffff);

			amdgpu_gfx_select_se_sh(adev, se_idx, sh_idx, 0xffffffff);

			queue_map = RREG32_SOC15(GC, 0, mmSPI_CSQ_WF_ACTIVE_STATUS);



			/*
@@ -820,7 +820,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid, 
		}

	}



	gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

	amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);

	soc15_grbm_select(adev, 0, 0, 0, 0);

	unlock_spi_csq_mutexes(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+7 −17
Original line number Diff line number Diff line
@@ -418,9 +418,9 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem) 
	if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)

		mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;



	switch (adev->asic_type) {

	case CHIP_ARCTURUS:

	case CHIP_ALDEBARAN:

	switch (adev->ip_versions[GC_HWIP][0]) {

	case IP_VERSION(9, 4, 1):

	case IP_VERSION(9, 4, 2):

		if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {

			if (bo_adev == adev) {

				if (uncached)
@@ -429,7 +429,7 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem) 
					mapping_flags |= AMDGPU_VM_MTYPE_CC;

				else

					mapping_flags |= AMDGPU_VM_MTYPE_RW;

				if (adev->asic_type == CHIP_ALDEBARAN &&

				if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) &&

				    adev->gmc.xgmi.connected_to_cpu)

					snoop = true;

			} else {
@@ -510,13 +510,13 @@ kfd_mem_dmamap_userptr(struct kgd_mem *mem, 
	struct ttm_tt *ttm = bo->tbo.ttm;

	int ret;



	if (WARN_ON(ttm->num_pages != src_ttm->num_pages))

		return -EINVAL;



	ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);

	if (unlikely(!ttm->sg))

		return -ENOMEM;



	if (WARN_ON(ttm->num_pages != src_ttm->num_pages))

		return -EINVAL;



	/* Same sequence as in amdgpu_ttm_tt_pin_userptr */

	ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,

					ttm->num_pages, 0,
@@ -1907,16 +1907,6 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( 
	 */

	mutex_lock(&mem->process_info->lock);



	/* Lock mmap-sem. If we find an invalid userptr BO, we can be

	 * sure that the MMU notifier is no longer running

	 * concurrently and the queues are actually stopped

	 */

	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {

		mmap_write_lock(current->mm);

		is_invalid_userptr = atomic_read(&mem->invalid);

		mmap_write_unlock(current->mm);

	}



	mutex_lock(&mem->lock);



	domain = mem->domain;