Commit 60ba8c5b authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-gt-next-2022-11-03' of...

Merge tag 'drm-intel-gt-next-2022-11-03' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

Driver Changes:

- Fix for #7306: [Arc A380] white flickering when using arc as a
  secondary gpu (Matt A)
- Add Wa_18017747507 for DG2 (Wayne)
- Avoid spurious WARN on DG1 due to incorrect cache_dirty flag
  (Niranjana, Matt A)
- Corrections to CS timestamp support for Gen5 and earlier (Ville)

- Fix a build error used with clang compiler on hwmon (GG)
- Improvements to LMEM handling with RPM (Anshuman, Matt A)
- Cleanups in dmabuf code (Mike)

- Selftest improvements (Matt A)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Y2N11wu175p6qeEN@jlahtine-mobl.ger.corp.intel.com
parents 441f0ec0 8f956e9a
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What:		/sys/devices/.../hwmon/hwmon<i>/in0_input
Date:		February 2023
KernelVersion:	6.2
Contact:	intel-gfx@lists.freedesktop.org
Description:	RO. Current Voltage in millivolt.

		Only supported for particular Intel i915 graphics platforms.

What:		/sys/devices/.../hwmon/hwmon<i>/power1_max
Date:		February 2023
KernelVersion:	6.2
Contact:	intel-gfx@lists.freedesktop.org
Description:	RW. Card reactive sustained  (PL1/Tau) power limit in microwatts.

		The power controller will throttle the operating frequency
		if the power averaged over a window (typically seconds)
		exceeds this limit.

		Only supported for particular Intel i915 graphics platforms.

What:		/sys/devices/.../hwmon/hwmon<i>/power1_rated_max
Date:		February 2023
KernelVersion:	6.2
Contact:	intel-gfx@lists.freedesktop.org
Description:	RO. Card default power limit (default TDP setting).

		Only supported for particular Intel i915 graphics platforms.

What:		/sys/devices/.../hwmon/hwmon<i>/power1_max_interval
Date:		February 2023
KernelVersion:	6.2
Contact:	intel-gfx@lists.freedesktop.org
Description:	RW. Sustained power limit interval (Tau in PL1/Tau) in
		milliseconds over which sustained power is averaged.

		Only supported for particular Intel i915 graphics platforms.

What:		/sys/devices/.../hwmon/hwmon<i>/power1_crit
Date:		February 2023
KernelVersion:	6.2
Contact:	intel-gfx@lists.freedesktop.org
Description:	RW. Card reactive critical (I1) power limit in microwatts.

		Card reactive critical (I1) power limit in microwatts is exposed
		for client products. The power controller will throttle the
		operating frequency if the power averaged over a window exceeds
		this limit.

		Only supported for particular Intel i915 graphics platforms.

What:		/sys/devices/.../hwmon/hwmon<i>/curr1_crit
Date:		February 2023
KernelVersion:	6.2
Contact:	intel-gfx@lists.freedesktop.org
Description:	RW. Card reactive critical (I1) power limit in milliamperes.

		Card reactive critical (I1) power limit in milliamperes is
		exposed for server products. The power controller will throttle
		the operating frequency if the power averaged over a window
		exceeds this limit.

		Only supported for particular Intel i915 graphics platforms.

What:		/sys/devices/.../hwmon/hwmon<i>/energy1_input
Date:		February 2023
KernelVersion:	6.2
Contact:	intel-gfx@lists.freedesktop.org
Description:	RO. Energy input of device or gt in microjoules.

		For i915 device level hwmon devices (name "i915") this
		reflects energy input for the entire device. For gt level
		hwmon devices (name "i915_gtN") this reflects energy input
		for the gt.

		Only supported for particular Intel i915 graphics platforms.
+1 −0
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@@ -10224,6 +10224,7 @@ Q: http://patchwork.freedesktop.org/project/intel-gfx/
B:	https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs
C:	irc://irc.oftc.net/intel-gfx
T:	git git://anongit.freedesktop.org/drm-intel
F:	Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
F:	Documentation/gpu/i915.rst
F:	drivers/gpu/drm/i915/
F:	include/drm/i915*
+22 −4
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@@ -57,10 +57,28 @@ config DRM_I915_PREEMPT_TIMEOUT
	default 640 # milliseconds
	help
	  How long to wait (in milliseconds) for a preemption event to occur
	  when submitting a new context via execlists. If the current context
	  does not hit an arbitration point and yield to HW before the timer
	  expires, the HW will be reset to allow the more important context
	  to execute.
	  when submitting a new context. If the current context does not hit
	  an arbitration point and yield to HW before the timer expires, the
	  HW will be reset to allow the more important context to execute.

	  This is adjustable via
	  /sys/class/drm/card?/engine/*/preempt_timeout_ms

	  May be 0 to disable the timeout.

	  The compiled in default may get overridden at driver probe time on
	  certain platforms and certain engines which will be reflected in the
	  sysfs control.

config DRM_I915_PREEMPT_TIMEOUT_COMPUTE
	int "Preempt timeout for compute engines (ms, jiffy granularity)"
	default 7500 # milliseconds
	help
	  How long to wait (in milliseconds) for a preemption event to occur
	  when submitting a new context to a compute capable engine. If the
	  current context does not hit an arbitration point and yield to HW
	  before the timer expires, the HW will be reset to allow the more
	  important context to execute.

	  This is adjustable via
	  /sys/class/drm/card?/engine/*/preempt_timeout_ms
+10 −4
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@@ -209,6 +209,9 @@ i915-y += gt/uc/intel_uc.o \
# graphics system controller (GSC) support
i915-y += gt/intel_gsc.o

# graphics hardware monitoring (HWMON) support
i915-$(CONFIG_HWMON) += i915_hwmon.o

# modesetting core code
i915-y += \
	display/hsw_ips.o \
@@ -310,15 +313,18 @@ i915-y += \

i915-y += i915_perf.o

# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
# Protected execution platform (PXP) support. Base support is required for HuC
i915-y += \
	pxp/intel_pxp.o \
	pxp/intel_pxp_tee.o \
	pxp/intel_pxp_huc.o

i915-$(CONFIG_DRM_I915_PXP) += \
	pxp/intel_pxp_cmd.o \
	pxp/intel_pxp_debugfs.o \
	pxp/intel_pxp_irq.o \
	pxp/intel_pxp_pm.o \
	pxp/intel_pxp_session.o \
	pxp/intel_pxp_tee.o
	pxp/intel_pxp_session.o

# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
+1 −0
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@@ -5,6 +5,7 @@

#include "gem/i915_gem_domain.h"
#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_lmem.h"
#include "gt/gen8_ppgtt.h"

#include "i915_drv.h"
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