Unverified Commit 488833cc authored by Palmer Dabbelt's avatar Palmer Dabbelt
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Merge patch series "dt-bindings: riscv: cpus: switch to unevaluatedProperties: false" 

Conor Dooley <conor@kernel.org> says:

From: Conor Dooley <conor.dooley@microchip.com>

Do the various bits needed to drop the additionalProperties: true that
we currently have in riscv/cpu.yaml, to permit actually enforcing what
people put in cpus nodes.

* b4-shazam-merge:
  dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
  dt-bindings: riscv: cpus: add a ref the common cpu schema

Link: https://lore.kernel.org/r/20230615-creamer-emu-ade0fa0bdb68@spud


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 91afbaaf 1ffe6ddc

Documentation/devicetree/bindings/riscv/cpus.yaml

+7 −1
Original line number Diff line number Diff line
@@ -23,6 +23,9 @@ description: | 
  two cores, each of which has two hyperthreads, could be described as

  having four harts.



allOf:

  - $ref: /schemas/cpu.yaml#



properties:

  compatible:

    oneOf:
@@ -98,6 +101,9 @@ properties: 
    $ref: /schemas/types.yaml#/definitions/string

    pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$



  # RISC-V has multiple properties for cache op block sizes as the sizes

  # differ between individual CBO extensions

  cache-op-block-size: false

  # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here

  timebase-frequency: false
@@ -137,7 +143,7 @@ required: 
  - riscv,isa

  - interrupt-controller



additionalProperties: true

unevaluatedProperties: false



examples:

  - |