Commit 47519d82 authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'amd-drm-next-6.1-2022-09-08' of https://gitlab.freedesktop.org/agd5f/linux into drm-next 



amd-drm-next-6.1-2022-09-08:

amdgpu:
- Mode2 reset for RDNA2
- Lots of new DC documentation
- Add documentation about different asic families
- DSC improvements
- Aldebaran fixes
- Misc spelling and grammar fixes
- GFXOFF stats support for vangogh
- DC frame size fixes
- NBIO 7.7 updates
- DCN 3.2 updates
- DCN 3.1.4 Updates
- SMU 13.x updates
- Misc bug fixes
- Rework DC register offset handling
- GC 11.x updates
- PSP 13.x updates
- SDMA 6.x updates
- GMC 11.x updates
- SR-IOV updates
- PSP fixes for TA unloading
- DSC passthrough support
- Misc code cleanups

amdkfd:
- ISA fixes for some GC 10.3 IPs
- Misc code cleanups

radeon:
- Delayed work flush fix
- Use time_after for some jiffies calculations

drm:
- DSC passthrough aux support

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220908155202.57862-1-alexander.deucher@amd.com
parents 89b03aea 780244a2

Documentation/gpu/amdgpu/apu-asic-info-table.csv

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Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version

Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3

Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0

Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2

Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1

SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1

Ryzen 5000 series, GREEN SARDINE, DCN 2.1, 9.3, VCN 2.2, 4.1.1

Ryzen 6000 Zen, YELLOW CARP, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3

Documentation/gpu/amdgpu/dgpu-asic-info-table.csv

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Product Name, Code Reference, DCN/DCE version, GC version, VCN version, SDMA version

AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series, HAINAN, --,  6, --, --

AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, --

AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND, DCE 6, 6, VCE 1 / UVD 3, --

AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN, DCE 6, 6, VCE 1 / UVD 3, --

AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M) /W4100 Series, VERDE, DCE 6, 6, VCE 1 / UVD 3, --

AMD Radeon HD M280X /M380 /7700 /8950 /W5100, BONAIRE, DCE 8, 7, VCE 2 / UVD 4.2, 1

AMD Radeon (R9|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE 2 / UVD 4.2, 1

AMD Radeon (TM) R(5|7) M315 /M340 /M360, TOPAZ, *, 8, --, 2

AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA, DCE 10, 8, VCE 3 / UVD 5, 3

AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3

Radeon RX 470 /480 /570 /580 /590 Series - AMD Radeon (TM) (Pro WX) 5100 /E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS10, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3

Radeon (TM) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3

Radeon (RX/Pro) 500 /540(X) /550 /640 /WX2100 /WX3100 /WX200 Series, POLARIS12, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3

Radeon (RX|TM) (PRO|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG MxGPU, VEGA10, DCE 12, 9.0.1, VCE 4.0.0 / UVD 7.0.0, 4.0.0

AMD Radeon (Pro) VII /MI50 /MI60, VEGA20, DCE 12, 9.4.0, VCE 4.1.0 / UVD 7.2.0, 4.2.0

MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2

MI200, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0

AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0

AMD Radeon (Pro) 5300 /5500XTB/5500(XT|M) /W5500M /W5500, NAVI14, DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0.2

AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN 3.0.0, 5.2.0

AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0.0, 5.2.2

AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4

AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5

Documentation/gpu/amdgpu/display/dc-glossary.rst

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@@ -170,7 +170,7 @@ consider asking in the amdgfx and update this page. 
    MC

      Memory Controller



    MPC

    MPC/MPCC

      Multiple pipes and plane combine



    MPO

Documentation/gpu/amdgpu/display/dcn-overview.rst

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@@ -124,6 +124,65 @@ depth format), bit-depth reduction/dithering would kick in. In OPP, we would 
also apply a regamma function to introduce the gamma removed earlier back.

Eventually, we output data in integer format at DIO.



AMD Hardware Pipeline

---------------------



When discussing graphics on Linux, the **pipeline** term can sometimes be

overloaded with multiple meanings, so it is important to define what we mean

when we say **pipeline**. In the DCN driver, we use the term **hardware

pipeline** or **pipeline** or just **pipe** as an abstraction to indicate a

sequence of DCN blocks instantiated to address some specific configuration. DC

core treats DCN blocks as individual resources, meaning we can build a pipeline

by taking resources for all individual hardware blocks to compose one pipeline.

In actuality, we can't connect an arbitrary block from one pipe to a block from

another pipe; they are routed linearly, except for DSC, which can be

arbitrarily assigned as needed. We have this pipeline concept for trying to

optimize bandwidth utilization.



.. kernel-figure:: pipeline_4k_no_split.svg



Additionally, let's take a look at parts of the DTN log (see

'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since

this log can help us to see part of this pipeline behavior in real-time::



 HUBP:  format  addr_hi  width  height ...

 [ 0]:      8h      81h   3840    2160

 [ 1]:      0h       0h      0       0

 [ 2]:      0h       0h      0       0

 [ 3]:      0h       0h      0       0

 [ 4]:      0h       0h      0       0

 ...

 MPCC:  OPP  DPP ...

 [ 0]:   0h   0h ...



The first thing to notice from the diagram and DTN log it is the fact that we

have different clock domains for each part of the DCN blocks. In this example,

we have just a single **pipeline** where the data flows from DCHUB to DIO, as

we intuitively expect. Nonetheless, DCN is flexible, as mentioned before, and

we can split this single pipe differently, as described in the below diagram:



.. kernel-figure:: pipeline_4k_split.svg



Now, if we inspect the DTN log again we can see some interesting changes::



 HUBP:  format  addr_hi  width  height ...

 [ 0]:      8h      81h   1920    2160 ...

 ...

 [ 4]:      0h       0h      0       0 ...

 [ 5]:      8h      81h   1920    2160 ...

 ...

 MPCC:  OPP  DPP ...

 [ 0]:   0h   0h ...

 [ 5]:   0h   5h ...



From the above example, we now split the display pipeline into two vertical

parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the

clock frequency in the DPP part. This is not only useful for saving power but

also to better handle the required throughput. The idea to keep in mind here is

that the pipe configuration can vary a lot according to the display

configuration, and it is the DML's responsibility to set up all required

configuration parameters for multiple scenarios supported by our hardware.



Global Sync

-----------

Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg

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