Commit 780244a2 authored Sep 07, 2022 by Tom St Denis Committed by Alex Deucher Sep 07, 2022

drm/amd/amdgpu: Add missing CGTS*TCC_DISABLE to 10.3 headers



The TCC_DISABLE registers were not included in the 10.3 headers and
instead just placed directly in the gfx_v10_0.c source.  This patch
adds them to the headers so tools like umr can scan them and support them.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 096e33f8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -9800,6 +9800,10 @@

		// addressBlock: gc_pwrdec
		// base address: 0x3c000
		#define mmCGTS_TCC_DISABLE 0x5006
		#define mmCGTS_TCC_DISABLE_BASE_IDX 1
		#define mmCGTS_USER_TCC_DISABLE 0x5007
		#define mmCGTS_USER_TCC_DISABLE_BASE_IDX 1
		#define mmSQ_ALU_CLK_CTRL 0x508e
		#define mmSQ_ALU_CLK_CTRL_BASE_IDX 1
		#define mmSQ_TEX_CLK_CTRL 0x508f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

+10 −0

Original line number	Diff line number	Diff line
		@@ -34547,6 +34547,16 @@


		// addressBlock: gc_pwrdec
		//CGTS_TCC_DISABLE
		#define CGTS_TCC_DISABLE__HI_TCC_DISABLE__SHIFT 0x8
		#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
		#define CGTS_TCC_DISABLE__HI_TCC_DISABLE_MASK 0x0000FF00L
		#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
		//CGTS_USER_TCC_DISABLE
		#define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE__SHIFT 0x8
		#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
		#define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE_MASK 0x0000FF00L
		#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
		//SQ_ALU_CLK_CTRL
		#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0
		#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10