drm/amd/powerplay: and smc dpm info struct for sienna_cichlid

  uint32_t     BoardReserved[5];

};

struct smudpm_i2c_controller_config_v3

{

  uint8_t   Enabled;

  uint8_t   Speed;

  uint8_t   SlaveAddress;

  uint8_t   ControllerPort;

  uint8_t   ControllerName;

  uint8_t   ThermalThrotter;

  uint8_t   I2cProtocol;

  uint8_t   PaddingConfig;

};

struct atom_smc_dpm_info_v4_9

{

  struct   atom_common_table_header  table_header;

  //SECTION: Gaming Clocks

  //uint32_t     GamingClk[6];

  // SECTION: I2C Control

  struct smudpm_i2c_controller_config_v3  I2cControllers[16];     

  uint8_t      GpioScl;  // GPIO Number for SCL Line, used only for CKSVII2C1

  uint8_t      GpioSda;  // GPIO Number for SDA Line, used only for CKSVII2C1

  uint8_t      FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off

  uint8_t      I2cSpare;

  // SECTION: SVI2 Board Parameters

  uint8_t      VddGfxVrMapping;   // Use VR_MAPPING* bitfields

  uint8_t      VddSocVrMapping;   // Use VR_MAPPING* bitfields

  uint8_t      VddMem0VrMapping;  // Use VR_MAPPING* bitfields

  uint8_t      VddMem1VrMapping;  // Use VR_MAPPING* bitfields

  uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

  uint8_t      SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

  uint8_t      VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

  uint8_t      MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

  // SECTION: Telemetry Settings

  uint16_t     GfxMaxCurrent;   // in Amps

  uint8_t      GfxOffset;       // in Amps

  uint8_t      Padding_TelemetryGfx;

  uint16_t     SocMaxCurrent;   // in Amps

  uint8_t      SocOffset;       // in Amps

  uint8_t      Padding_TelemetrySoc;

  uint16_t     Mem0MaxCurrent;   // in Amps

  uint8_t      Mem0Offset;       // in Amps

  uint8_t      Padding_TelemetryMem0;

  uint16_t     Mem1MaxCurrent;   // in Amps

  uint8_t      Mem1Offset;       // in Amps

  uint8_t      Padding_TelemetryMem1;

  uint32_t     MvddRatio; // This is used for MVDD  Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)

  // SECTION: GPIO Settings

  uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching

  uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching

  uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event

  uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event

  uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event 

  uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event 

  uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event

  uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR

  // LED Display Settings

  uint8_t      LedPin0;         // GPIO number for LedPin[0]

  uint8_t      LedPin1;         // GPIO number for LedPin[1]

  uint8_t      LedPin2;         // GPIO number for LedPin[2]

  uint8_t      LedEnableMask;

  uint8_t      LedPcie;        // GPIO number for PCIE results

  uint8_t      LedError;       // GPIO number for Error Cases

  uint8_t      LedSpare1[2];

  // SECTION: Clock Spread Spectrum

  // GFXCLK PLL Spread Spectrum

  uint8_t      PllGfxclkSpreadEnabled;   // on or off

  uint8_t      PllGfxclkSpreadPercent;   // Q4.4

  uint16_t     PllGfxclkSpreadFreq;      // kHz

  // GFXCLK DFLL Spread Spectrum

  uint8_t      DfllGfxclkSpreadEnabled;   // on or off

  uint8_t      DfllGfxclkSpreadPercent;   // Q4.4

  uint16_t     DfllGfxclkSpreadFreq;      // kHz

  // UCLK Spread Spectrum

  uint8_t      UclkSpreadEnabled;   // on or off

  uint8_t      UclkSpreadPercent;   // Q4.4

  uint16_t     UclkSpreadFreq;      // kHz

  // FCLK Spread Spectrum

  uint8_t      FclkSpreadEnabled;   // on or off

  uint8_t      FclkSpreadPercent;   // Q4.4

  uint16_t     FclkSpreadFreq;      // kHz

  // Section: Memory Config

  uint32_t     MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 

  uint8_t      DramBitWidth; // For DRAM use only.  See Dram Bit width type defines

  uint8_t      PaddingMem1[3];

  // Section: Total Board Power

  uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power

  uint16_t     BoardPowerPadding; 

  // SECTION: XGMI Training

  uint8_t      XgmiLinkSpeed   [4];

  uint8_t      XgmiLinkWidth   [4];

  uint16_t     XgmiFclkFreq    [4];

  uint16_t     XgmiSocVoltage  [4];

  // SECTION: Board Reserved

  uint32_t     BoardReserved[16];

};

/* 

  ***************************************************************************

    Data Table asic_profiling_info  structure