Commit 4468a344 authored by Alex Elder's avatar Alex Elder Committed by Jakub Kicinski
Browse files

net: ipa: define some IPA endpoint register fields 



Define the fields for the ENDP_INIT_CTRL, ENDP_INIT_CFG, ENDP_INIT_NAT,
ENDP_INIT_HDR, and ENDP_INIT_HDR_EXT IPA registers for all supported
IPA versions.

Create enumerated types to identify fields for these IPA registers.
Use IPA_REG_STRIDE_FIELDS() to specify the field mask values defined
for these registers, for each supported version of IPA.

Move ipa_header_size_encoded() and ipa_metadata_offset_encoded() out
of "ipa_reg.h" and into "ipa_endpoint.c".  Change them so they take
an additional ipa_reg structure argument, and use ipa_reg_encode()
to encode the parts of the header size and offset prior to writing
to the register.  Change their names to be verbs rather than nouns.

Use ipa_reg_encode(), ipa_reg_bit, and ipa_reg_field_max() to
manipulate values to be written to these registers, remove the
definition of the no-longer-used *_FMASK symbols.

Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 1c418c4a

drivers/net/ipa/ipa_endpoint.c

+66 −20
Original line number Diff line number Diff line
@@ -310,6 +310,7 @@ ipa_endpoint_init_ctrl(struct ipa_endpoint *endpoint, bool suspend_delay) 
{

	struct ipa *ipa = endpoint->ipa;

	const struct ipa_reg *reg;

	u32 field_id;

	u32 offset;

	bool state;

	u32 mask;
@@ -321,10 +322,12 @@ ipa_endpoint_init_ctrl(struct ipa_endpoint *endpoint, bool suspend_delay) 
		WARN_ON(ipa->version >= IPA_VERSION_4_0);



	reg = ipa_reg(ipa, ENDP_INIT_CTRL);

	mask = endpoint->toward_ipa ? ENDP_DELAY_FMASK : ENDP_SUSPEND_FMASK;

	offset = ipa_reg_n_offset(reg, endpoint->endpoint_id);

	val = ioread32(ipa->reg_virt + offset);



	field_id = endpoint->toward_ipa ? ENDP_DELAY : ENDP_SUSPEND;

	mask = ipa_reg_bit(reg, field_id);



	state = !!(val & mask);



	/* Don't bother if it's already in the requested state */
@@ -516,10 +519,8 @@ static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint) 
			u32 off;



			/* Checksum header offset is in 4-byte units */

			off = sizeof(struct rmnet_map_header);

			off /= sizeof(u32);

			val |= u32_encode_bits(off,

					       CS_METADATA_HDR_OFFSET_FMASK);

			off = sizeof(struct rmnet_map_header) / sizeof(u32);

			val |= ipa_reg_encode(reg, CS_METADATA_HDR_OFFSET, off);



			enabled = version < IPA_VERSION_4_5

					? IPA_CS_OFFLOAD_UL
@@ -532,7 +533,7 @@ static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint) 
	} else {

		enabled = IPA_CS_OFFLOAD_NONE;

	}

	val |= u32_encode_bits(enabled, CS_OFFLOAD_EN_FMASK);

	val |= ipa_reg_encode(reg, CS_OFFLOAD_EN, enabled);

	/* CS_GEN_QMB_MASTER_SEL is 0 */



	iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id));
@@ -549,7 +550,7 @@ static void ipa_endpoint_init_nat(struct ipa_endpoint *endpoint) 
		return;



	reg = ipa_reg(ipa, ENDP_INIT_NAT);

	val = u32_encode_bits(IPA_NAT_BYPASS, NAT_EN_FMASK);

	val = ipa_reg_encode(reg, NAT_EN, IPA_NAT_BYPASS);



	iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, endpoint_id));

}
@@ -575,6 +576,50 @@ ipa_qmap_header_size(enum ipa_version version, struct ipa_endpoint *endpoint) 
	return header_size;

}



/* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */

static u32 ipa_header_size_encode(enum ipa_version version,

				  const struct ipa_reg *reg, u32 header_size)

{

	u32 field_max = ipa_reg_field_max(reg, HDR_LEN);

	u32 val;



	/* We know field_max can be used as a mask (2^n - 1) */

	val = ipa_reg_encode(reg, HDR_LEN, header_size & field_max);

	if (version < IPA_VERSION_4_5) {

		WARN_ON(header_size > field_max);

		return val;

	}



	/* IPA v4.5 adds a few more most-significant bits */

	header_size >>= hweight32(field_max);

	WARN_ON(header_size > ipa_reg_field_max(reg, HDR_LEN_MSB));

	val |= ipa_reg_encode(reg, HDR_LEN_MSB, header_size);



	return val;

}



/* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */

static u32 ipa_metadata_offset_encode(enum ipa_version version,

				      const struct ipa_reg *reg, u32 offset)

{

	u32 field_max = ipa_reg_field_max(reg, HDR_OFST_METADATA);

	u32 val;



	/* We know field_max can be used as a mask (2^n - 1) */

	val = ipa_reg_encode(reg, HDR_OFST_METADATA, offset);

	if (version < IPA_VERSION_4_5) {

		WARN_ON(offset > field_max);

		return val;

	}



	/* IPA v4.5 adds a few more most-significant bits */

	offset >>= hweight32(field_max);

	WARN_ON(offset > ipa_reg_field_max(reg, HDR_OFST_METADATA_MSB));

	val |= ipa_reg_encode(reg, HDR_OFST_METADATA_MSB, offset);



	return val;

}



/**

 * ipa_endpoint_init_hdr() - Initialize HDR endpoint configuration register

 * @endpoint:	Endpoint pointer
@@ -609,7 +654,7 @@ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint) 
		size_t header_size;



		header_size = ipa_qmap_header_size(version, endpoint);

		val = ipa_header_size_encoded(version, header_size);

		val = ipa_header_size_encode(version, reg, header_size);



		/* Define how to fill fields in a received QMAP header */

		if (!endpoint->toward_ipa) {
@@ -617,19 +662,19 @@ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint) 


			/* Where IPA will write the metadata value */

			off = offsetof(struct rmnet_map_header, mux_id);

			val |= ipa_metadata_offset_encoded(version, off);

			val |= ipa_metadata_offset_encode(version, reg, off);



			/* Where IPA will write the length */

			off = offsetof(struct rmnet_map_header, pkt_len);

			/* Upper bits are stored in HDR_EXT with IPA v4.5 */

			if (version >= IPA_VERSION_4_5)

				off &= field_mask(HDR_OFST_PKT_SIZE_FMASK);

				off &= ipa_reg_field_max(reg, HDR_OFST_PKT_SIZE);



			val |= HDR_OFST_PKT_SIZE_VALID_FMASK;

			val |= u32_encode_bits(off, HDR_OFST_PKT_SIZE_FMASK);

			val |= ipa_reg_bit(reg, HDR_OFST_PKT_SIZE_VALID);

			val |= ipa_reg_encode(reg, HDR_OFST_PKT_SIZE, off);

		}

		/* For QMAP TX, metadata offset is 0 (modem assumes this) */

		val |= HDR_OFST_METADATA_VALID_FMASK;

		val |= ipa_reg_bit(reg, HDR_OFST_METADATA_VALID);



		/* HDR_ADDITIONAL_CONST_LEN is 0; (RX only) */

		/* HDR_A5_MUX is 0 */
@@ -651,7 +696,7 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint) 
	reg = ipa_reg(ipa, ENDP_INIT_HDR_EXT);

	if (endpoint->config.qmap) {

		/* We have a header, so we must specify its endianness */

		val |= HDR_ENDIANNESS_FMASK;	/* big endian */

		val |= ipa_reg_bit(reg, HDR_ENDIANNESS);	/* big endian */



		/* A QMAP header contains a 6 bit pad field at offset 0.

		 * The RMNet driver assumes this field is meaningful in
@@ -661,16 +706,16 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint) 
		 * (although 0) should be ignored.

		 */

		if (!endpoint->toward_ipa) {

			val |= HDR_TOTAL_LEN_OR_PAD_VALID_FMASK;

			val |= ipa_reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID);

			/* HDR_TOTAL_LEN_OR_PAD is 0 (pad, not total_len) */

			val |= HDR_PAYLOAD_LEN_INC_PADDING_FMASK;

			val |= ipa_reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING);

			/* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0 */

		}

	}



	/* HDR_PAYLOAD_LEN_INC_PADDING is 0 */

	if (!endpoint->toward_ipa)

		val |= u32_encode_bits(pad_align, HDR_PAD_TO_ALIGNMENT_FMASK);

		val |= ipa_reg_encode(reg, HDR_PAD_TO_ALIGNMENT, pad_align);



	/* IPA v4.5 adds some most-significant bits to a few fields,

	 * two of which are defined in the HDR (not HDR_EXT) register.
@@ -678,12 +723,13 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint) 
	if (ipa->version >= IPA_VERSION_4_5) {

		/* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0, so MSB is 0 */

		if (endpoint->config.qmap && !endpoint->toward_ipa) {

			u32 mask = ipa_reg_field_max(reg, HDR_OFST_PKT_SIZE);

			u32 off;     /* Field offset within header */



			off = offsetof(struct rmnet_map_header, pkt_len);

			off >>= hweight32(HDR_OFST_PKT_SIZE_FMASK);

			val |= u32_encode_bits(off,

					       HDR_OFST_PKT_SIZE_MSB_FMASK);

			/* Low bits are in the ENDP_INIT_HDR register */

			off >>= hweight32(mask);

			val |= ipa_reg_encode(reg, HDR_OFST_PKT_SIZE_MSB, off);

			/* HDR_ADDITIONAL_CONST_LEN is 0 so MSB is 0 */

		}

	}

drivers/net/ipa/ipa_reg.h

+37 −73
Original line number Diff line number Diff line
@@ -371,16 +371,18 @@ enum ipa_reg_rsrc_grp_rsrc_type_field_id { 
};



/* ENDP_INIT_CTRL register */

/* Valid only for RX (IPA producer) endpoints (do not use for IPA v4.0+) */

#define ENDP_SUSPEND_FMASK			GENMASK(0, 0)

/* Valid only for TX (IPA consumer) endpoints */

#define ENDP_DELAY_FMASK			GENMASK(1, 1)

enum ipa_reg_endp_init_ctrl_field_id {

	ENDP_SUSPEND,					/* Not v4.0+ */

	ENDP_DELAY,					/* Not v4.2+ */

};



/* ENDP_INIT_CFG register */

#define FRAG_OFFLOAD_EN_FMASK			GENMASK(0, 0)

#define CS_OFFLOAD_EN_FMASK			GENMASK(2, 1)

#define CS_METADATA_HDR_OFFSET_FMASK		GENMASK(6, 3)

#define CS_GEN_QMB_MASTER_SEL_FMASK		GENMASK(8, 8)

enum ipa_reg_endp_init_cfg_field_id {

	FRAG_OFFLOAD_EN,

	CS_OFFLOAD_EN,

	CS_METADATA_HDR_OFFSET,

	CS_GEN_QMB_MASTER_SEL,

};



/** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */

enum ipa_cs_offload_en {
@@ -391,7 +393,9 @@ enum ipa_cs_offload_en { 
};



/* ENDP_INIT_NAT register */

#define NAT_EN_FMASK				GENMASK(1, 0)

enum ipa_reg_endp_init_nat_field_id {

	NAT_EN,

};



/** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */

enum ipa_nat_en {
@@ -401,72 +405,32 @@ enum ipa_nat_en { 
};



/* ENDP_INIT_HDR register */

#define HDR_LEN_FMASK				GENMASK(5, 0)

#define HDR_OFST_METADATA_VALID_FMASK		GENMASK(6, 6)

#define HDR_OFST_METADATA_FMASK			GENMASK(12, 7)

#define HDR_ADDITIONAL_CONST_LEN_FMASK		GENMASK(18, 13)

#define HDR_OFST_PKT_SIZE_VALID_FMASK		GENMASK(19, 19)

#define HDR_OFST_PKT_SIZE_FMASK			GENMASK(25, 20)

/* The next field is not present for IPA v4.9+ */

#define HDR_A5_MUX_FMASK			GENMASK(26, 26)

#define HDR_LEN_INC_DEAGG_HDR_FMASK		GENMASK(27, 27)

/* The next field is not present for IPA v4.5+ */

#define HDR_METADATA_REG_VALID_FMASK		GENMASK(28, 28)

/* The next two fields are present for IPA v4.5+ */

#define HDR_LEN_MSB_FMASK			GENMASK(29, 28)

#define HDR_OFST_METADATA_MSB_FMASK		GENMASK(31, 30)



/* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */

static inline u32 ipa_header_size_encoded(enum ipa_version version,

					  u32 header_size)

{

	u32 size = header_size & field_mask(HDR_LEN_FMASK);

	u32 val;



	val = u32_encode_bits(size, HDR_LEN_FMASK);

	if (version < IPA_VERSION_4_5) {

		WARN_ON(header_size != size);

		return val;

	}



	/* IPA v4.5 adds a few more most-significant bits */

	size = header_size >> hweight32(HDR_LEN_FMASK);

	val |= u32_encode_bits(size, HDR_LEN_MSB_FMASK);



	return val;

}



/* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */

static inline u32 ipa_metadata_offset_encoded(enum ipa_version version,

					      u32 offset)

{

	u32 off = offset & field_mask(HDR_OFST_METADATA_FMASK);

	u32 val;



	val = u32_encode_bits(off, HDR_OFST_METADATA_FMASK);

	if (version < IPA_VERSION_4_5) {

		WARN_ON(offset != off);

		return val;

	}



	/* IPA v4.5 adds a few more most-significant bits */

	off = offset >> hweight32(HDR_OFST_METADATA_FMASK);

	val |= u32_encode_bits(off, HDR_OFST_METADATA_MSB_FMASK);



	return val;

}

enum ipa_reg_endp_init_hdr_field_id {

	HDR_LEN,

	HDR_OFST_METADATA_VALID,

	HDR_OFST_METADATA,

	HDR_ADDITIONAL_CONST_LEN,

	HDR_OFST_PKT_SIZE_VALID,

	HDR_OFST_PKT_SIZE,

	HDR_A5_MUX,					/* Not v4.9+ */

	HDR_LEN_INC_DEAGG_HDR,

	HDR_METADATA_REG_VALID,				/* Not v4.5+ */

	HDR_LEN_MSB,					/* v4.5+ */

	HDR_OFST_METADATA_MSB,				/* v4.5+ */

};



/* ENDP_INIT_HDR_EXT register */

#define HDR_ENDIANNESS_FMASK			GENMASK(0, 0)

#define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK	GENMASK(1, 1)

#define HDR_TOTAL_LEN_OR_PAD_FMASK		GENMASK(2, 2)

#define HDR_PAYLOAD_LEN_INC_PADDING_FMASK	GENMASK(3, 3)

#define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK	GENMASK(9, 4)

#define HDR_PAD_TO_ALIGNMENT_FMASK		GENMASK(13, 10)

/* The next three fields are present for IPA v4.5+ */

#define HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_FMASK	GENMASK(17, 16)

#define HDR_OFST_PKT_SIZE_MSB_FMASK		GENMASK(19, 18)

#define HDR_ADDITIONAL_CONST_LEN_MSB_FMASK	GENMASK(21, 20)

enum ipa_reg_endp_init_hdr_ext_field_id {

	HDR_ENDIANNESS,

	HDR_TOTAL_LEN_OR_PAD_VALID,

	HDR_TOTAL_LEN_OR_PAD,

	HDR_PAYLOAD_LEN_INC_PADDING,

	HDR_TOTAL_LEN_OR_PAD_OFFSET,

	HDR_PAD_TO_ALIGNMENT,

	HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB,		/* v4.5+ */

	HDR_OFST_PKT_SIZE_MSB,				/* v4.5+ */

	HDR_ADDITIONAL_CONST_LEN_MSB,			/* v4.5+ */

};



/* ENDP_INIT_MODE register */

#define MODE_FMASK				GENMASK(2, 0)

drivers/net/ipa/reg/ipa_reg-v3.1.c

+48 −5
Original line number Diff line number Diff line
@@ -238,15 +238,58 @@ static const u32 ipa_reg_dst_rsrc_grp_67_rsrc_type_fmask[] = { 
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,

		      0x0000050c, 0x0020);



IPA_REG_STRIDE(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);

static const u32 ipa_reg_endp_init_ctrl_fmask[] = {

	[ENDP_SUSPEND]					= BIT(0),

	[ENDP_DELAY]					= BIT(1),

						/* Bits 2-31 reserved */

};



IPA_REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);



IPA_REG_STRIDE(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);

static const u32 ipa_reg_endp_init_cfg_fmask[] = {

	[FRAG_OFFLOAD_EN]				= BIT(0),

	[CS_OFFLOAD_EN]					= GENMASK(2, 1),

	[CS_METADATA_HDR_OFFSET]			= GENMASK(6, 3),

						/* Bit 7 reserved */

	[CS_GEN_QMB_MASTER_SEL]				= BIT(8),

						/* Bits 9-31 reserved */

};



IPA_REG_STRIDE(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);

IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);



static const u32 ipa_reg_endp_init_nat_fmask[] = {

	[NAT_EN]					= GENMASK(1, 0),

						/* Bits 2-31 reserved */

};



IPA_REG_STRIDE(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);

IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);



static const u32 ipa_reg_endp_init_hdr_fmask[] = {

	[HDR_LEN]					= GENMASK(5, 0),

	[HDR_OFST_METADATA_VALID]			= BIT(6),

	[HDR_OFST_METADATA]				= GENMASK(12, 7),

	[HDR_ADDITIONAL_CONST_LEN]			= GENMASK(18, 13),

	[HDR_OFST_PKT_SIZE_VALID]			= BIT(19),

	[HDR_OFST_PKT_SIZE]				= GENMASK(25, 20),

	[HDR_A5_MUX]					= BIT(26),

	[HDR_LEN_INC_DEAGG_HDR]				= BIT(27),

	[HDR_METADATA_REG_VALID]			= BIT(28),

						/* Bits 29-31 reserved */

};



IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);



static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {

	[HDR_ENDIANNESS]				= BIT(0),

	[HDR_TOTAL_LEN_OR_PAD_VALID]			= BIT(1),

	[HDR_TOTAL_LEN_OR_PAD]				= BIT(2),

	[HDR_PAYLOAD_LEN_INC_PADDING]			= BIT(3),

	[HDR_TOTAL_LEN_OR_PAD_OFFSET]			= GENMASK(9, 4),

	[HDR_PAD_TO_ALIGNMENT]				= GENMASK(13, 10),

						/* Bits 14-31 reserved */

};



IPA_REG_STRIDE(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);

IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);



IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,

	       0x00000818, 0x0070);

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

+48 −5
Original line number Diff line number Diff line
@@ -217,15 +217,58 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,

		      0x00000504, 0x0020);



IPA_REG_STRIDE(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);

static const u32 ipa_reg_endp_init_ctrl_fmask[] = {

	[ENDP_SUSPEND]					= BIT(0),

	[ENDP_DELAY]					= BIT(1),

						/* Bits 2-31 reserved */

};



IPA_REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);



IPA_REG_STRIDE(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);

static const u32 ipa_reg_endp_init_cfg_fmask[] = {

	[FRAG_OFFLOAD_EN]				= BIT(0),

	[CS_OFFLOAD_EN]					= GENMASK(2, 1),

	[CS_METADATA_HDR_OFFSET]			= GENMASK(6, 3),

						/* Bit 7 reserved */

	[CS_GEN_QMB_MASTER_SEL]				= BIT(8),

						/* Bits 9-31 reserved */

};



IPA_REG_STRIDE(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);

IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);



static const u32 ipa_reg_endp_init_nat_fmask[] = {

	[NAT_EN]					= GENMASK(1, 0),

						/* Bits 2-31 reserved */

};



IPA_REG_STRIDE(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);

IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);



static const u32 ipa_reg_endp_init_hdr_fmask[] = {

	[HDR_LEN]					= GENMASK(5, 0),

	[HDR_OFST_METADATA_VALID]			= BIT(6),

	[HDR_OFST_METADATA]				= GENMASK(12, 7),

	[HDR_ADDITIONAL_CONST_LEN]			= GENMASK(18, 13),

	[HDR_OFST_PKT_SIZE_VALID]			= BIT(19),

	[HDR_OFST_PKT_SIZE]				= GENMASK(25, 20),

	[HDR_A5_MUX]					= BIT(26),

	[HDR_LEN_INC_DEAGG_HDR]				= BIT(27),

	[HDR_METADATA_REG_VALID]			= BIT(28),

						/* Bits 29-31 reserved */

};



IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);



static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {

	[HDR_ENDIANNESS]				= BIT(0),

	[HDR_TOTAL_LEN_OR_PAD_VALID]			= BIT(1),

	[HDR_TOTAL_LEN_OR_PAD]				= BIT(2),

	[HDR_PAYLOAD_LEN_INC_PADDING]			= BIT(3),

	[HDR_TOTAL_LEN_OR_PAD_OFFSET]			= GENMASK(9, 4),

	[HDR_PAD_TO_ALIGNMENT]				= GENMASK(13, 10),

						/* Bits 14-31 reserved */

};



IPA_REG_STRIDE(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);

IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);



IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,

	       0x00000818, 0x0070);

drivers/net/ipa/reg/ipa_reg-v4.11.c

+45 −4
Original line number Diff line number Diff line
@@ -274,13 +274,54 @@ static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,

		      0x00000504, 0x0020);



IPA_REG_STRIDE(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);

static const u32 ipa_reg_endp_init_cfg_fmask[] = {

	[FRAG_OFFLOAD_EN]				= BIT(0),

	[CS_OFFLOAD_EN]					= GENMASK(2, 1),

	[CS_METADATA_HDR_OFFSET]			= GENMASK(6, 3),

						/* Bit 7 reserved */

	[CS_GEN_QMB_MASTER_SEL]				= BIT(8),

						/* Bits 9-31 reserved */

};



IPA_REG_STRIDE(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);

IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);



IPA_REG_STRIDE(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);

static const u32 ipa_reg_endp_init_nat_fmask[] = {

	[NAT_EN]					= GENMASK(1, 0),

						/* Bits 2-31 reserved */

};



IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);



static const u32 ipa_reg_endp_init_hdr_fmask[] = {

	[HDR_LEN]					= GENMASK(5, 0),

	[HDR_OFST_METADATA_VALID]			= BIT(6),

	[HDR_OFST_METADATA]				= GENMASK(12, 7),

	[HDR_ADDITIONAL_CONST_LEN]			= GENMASK(18, 13),

	[HDR_OFST_PKT_SIZE_VALID]			= BIT(19),

	[HDR_OFST_PKT_SIZE]				= GENMASK(25, 20),

						/* Bit 26 reserved */

	[HDR_LEN_INC_DEAGG_HDR]				= BIT(27),

	[HDR_LEN_MSB]					= GENMASK(29, 28),

	[HDR_OFST_METADATA_MSB]				= GENMASK(31, 30),

};



IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);



static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = {

	[HDR_ENDIANNESS]				= BIT(0),

	[HDR_TOTAL_LEN_OR_PAD_VALID]			= BIT(1),

	[HDR_TOTAL_LEN_OR_PAD]				= BIT(2),

	[HDR_PAYLOAD_LEN_INC_PADDING]			= BIT(3),

	[HDR_TOTAL_LEN_OR_PAD_OFFSET]			= GENMASK(9, 4),

	[HDR_PAD_TO_ALIGNMENT]				= GENMASK(13, 10),

						/* Bits 14-15 reserved */

	[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB]		= GENMASK(17, 16),

	[HDR_OFST_PKT_SIZE_MSB]				= GENMASK(19, 18),

	[HDR_ADDITIONAL_CONST_LEN_MSB]			= GENMASK(21, 20),

						/* Bits 22-31 reserved */

};



IPA_REG_STRIDE(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);

IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);



IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,

	       0x00000818, 0x0070);