Commit 1c418c4a authored by Alex Elder's avatar Alex Elder Committed by Jakub Kicinski
Browse files

net: ipa: define resource group/type IPA register fields 



Define the fields for the {SRC,DST}_RSRC_GRP_{01,23,45,67}_RSRC_TYPE
IPA registers for all supported IPA versions.

Create enumerated types to identify fields for these IPA registers.
Use IPA_REG_STRIDE_FIELDS() to specify the field mask values defined
for these registers, for each supported version of IPA.

Use ipa_reg_encode() to build up the values to be written to these
registers.

Remove the definition of the no-longer-used *_FMASK symbols.

Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 9265a4f0

drivers/net/ipa/ipa_reg.h

+6 −4
Original line number Diff line number Diff line
@@ -363,10 +363,12 @@ enum ipa_pulse_gran { 
};



/* {SRC,DST}_RSRC_GRP_{01,23,45,67}_RSRC_TYPE registers */

#define X_MIN_LIM_FMASK				GENMASK(5, 0)

#define X_MAX_LIM_FMASK				GENMASK(13, 8)

#define Y_MIN_LIM_FMASK				GENMASK(21, 16)

#define Y_MAX_LIM_FMASK				GENMASK(29, 24)

enum ipa_reg_rsrc_grp_rsrc_type_field_id {

	X_MIN_LIM,

	X_MAX_LIM,

	Y_MIN_LIM,

	Y_MAX_LIM,

};



/* ENDP_INIT_CTRL register */

/* Valid only for RX (IPA producer) endpoints (do not use for IPA v4.0+) */

drivers/net/ipa/ipa_resource.c

+23 −30
Original line number Diff line number Diff line
@@ -69,20 +69,21 @@ static bool ipa_resource_limits_valid(struct ipa *ipa, 
}



static void

ipa_resource_config_common(struct ipa *ipa, u32 offset,

ipa_resource_config_common(struct ipa *ipa, u32 resource_type,

			   const struct ipa_reg *reg,

			   const struct ipa_resource_limits *xlimits,

			   const struct ipa_resource_limits *ylimits)

{

	u32 val;



	val = u32_encode_bits(xlimits->min, X_MIN_LIM_FMASK);

	val |= u32_encode_bits(xlimits->max, X_MAX_LIM_FMASK);

	val = ipa_reg_encode(reg, X_MIN_LIM, xlimits->min);

	val |= ipa_reg_encode(reg, X_MAX_LIM, xlimits->max);

	if (ylimits) {

		val |= u32_encode_bits(ylimits->min, Y_MIN_LIM_FMASK);

		val |= u32_encode_bits(ylimits->max, Y_MAX_LIM_FMASK);

		val |= ipa_reg_encode(reg, Y_MIN_LIM, ylimits->min);

		val |= ipa_reg_encode(reg, Y_MAX_LIM, ylimits->max);

	}



	iowrite32(val, ipa->reg_virt + offset);

	iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, resource_type));

}



static void ipa_resource_config_src(struct ipa *ipa, u32 resource_type,
@@ -92,38 +93,34 @@ static void ipa_resource_config_src(struct ipa *ipa, u32 resource_type, 
	const struct ipa_resource_limits *ylimits;

	const struct ipa_resource *resource;

	const struct ipa_reg *reg;

	u32 offset;



	resource = &data->resource_src[resource_type];



	reg = ipa_reg(ipa, SRC_RSRC_GRP_01_RSRC_TYPE);

	offset = ipa_reg_n_offset(reg, resource_type);

	ylimits = group_count == 1 ? NULL : &resource->limits[1];

	ipa_resource_config_common(ipa, offset, &resource->limits[0], ylimits);



	ipa_resource_config_common(ipa, resource_type, reg,

				   &resource->limits[0], ylimits);

	if (group_count < 3)

		return;



	reg = ipa_reg(ipa, SRC_RSRC_GRP_23_RSRC_TYPE);

	offset = ipa_reg_n_offset(reg, resource_type);

	ylimits = group_count == 3 ? NULL : &resource->limits[3];

	ipa_resource_config_common(ipa, offset, &resource->limits[2], ylimits);



	ipa_resource_config_common(ipa, resource_type, reg,

				   &resource->limits[2], ylimits);

	if (group_count < 5)

		return;



	reg = ipa_reg(ipa, SRC_RSRC_GRP_45_RSRC_TYPE);

	offset = ipa_reg_n_offset(reg, resource_type);

	ylimits = group_count == 5 ? NULL : &resource->limits[5];

	ipa_resource_config_common(ipa, offset, &resource->limits[4], ylimits);



	ipa_resource_config_common(ipa, resource_type, reg,

				   &resource->limits[4], ylimits);

	if (group_count < 7)

		return;



	reg = ipa_reg(ipa, SRC_RSRC_GRP_67_RSRC_TYPE);

	offset = ipa_reg_n_offset(reg, resource_type);

	ylimits = group_count == 7 ? NULL : &resource->limits[7];

	ipa_resource_config_common(ipa, offset, &resource->limits[6], ylimits);

	ipa_resource_config_common(ipa, resource_type, reg,

				   &resource->limits[6], ylimits);

}



static void ipa_resource_config_dst(struct ipa *ipa, u32 resource_type,
@@ -133,38 +130,34 @@ static void ipa_resource_config_dst(struct ipa *ipa, u32 resource_type, 
	const struct ipa_resource_limits *ylimits;

	const struct ipa_resource *resource;

	const struct ipa_reg *reg;

	u32 offset;



	resource = &data->resource_dst[resource_type];



	reg = ipa_reg(ipa, DST_RSRC_GRP_01_RSRC_TYPE);

	offset = ipa_reg_n_offset(reg, resource_type);

	ylimits = group_count == 1 ? NULL : &resource->limits[1];

	ipa_resource_config_common(ipa, offset, &resource->limits[0], ylimits);



	ipa_resource_config_common(ipa, resource_type, reg,

				   &resource->limits[0], ylimits);

	if (group_count < 3)

		return;



	reg = ipa_reg(ipa, DST_RSRC_GRP_23_RSRC_TYPE);

	offset = ipa_reg_n_offset(reg, resource_type);

	ylimits = group_count == 3 ? NULL : &resource->limits[3];

	ipa_resource_config_common(ipa, offset, &resource->limits[2], ylimits);



	ipa_resource_config_common(ipa, resource_type, reg,

				   &resource->limits[2], ylimits);

	if (group_count < 5)

		return;



	reg = ipa_reg(ipa, DST_RSRC_GRP_45_RSRC_TYPE);

	offset = ipa_reg_n_offset(reg, resource_type);

	ylimits = group_count == 5 ? NULL : &resource->limits[5];

	ipa_resource_config_common(ipa, offset, &resource->limits[4], ylimits);



	ipa_resource_config_common(ipa, resource_type, reg,

				   &resource->limits[4], ylimits);

	if (group_count < 7)

		return;



	reg = ipa_reg(ipa, DST_RSRC_GRP_67_RSRC_TYPE);

	offset = ipa_reg_n_offset(reg, resource_type);

	ylimits = group_count == 7 ? NULL : &resource->limits[7];

	ipa_resource_config_common(ipa, offset, &resource->limits[6], ylimits);

	ipa_resource_config_common(ipa, resource_type, reg,

				   &resource->limits[6], ylimits);

}



/* Configure resources; there is no ipa_resource_deconfig() */

drivers/net/ipa/reg/ipa_reg-v3.1.c

+104 −16
Original line number Diff line number Diff line
@@ -126,28 +126,116 @@ static const u32 ipa_reg_counter_cfg_fmask[] = { 


IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);



IPA_REG_STRIDE(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,

static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,

		      0x00000400, 0x0020);



IPA_REG_STRIDE(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,

static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,

		      0x00000404, 0x0020);



IPA_REG_STRIDE(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,

static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,

		      0x00000408, 0x0020);



IPA_REG_STRIDE(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,

static const u32 ipa_reg_src_rsrc_grp_67_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,

		      0x0000040c, 0x0020);



IPA_REG_STRIDE(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,

static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,

		      0x00000500, 0x0020);



IPA_REG_STRIDE(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,

static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,

		      0x00000504, 0x0020);



IPA_REG_STRIDE(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,

static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,

		      0x00000508, 0x0020);



IPA_REG_STRIDE(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,

static const u32 ipa_reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,

		      0x0000050c, 0x0020);



IPA_REG_STRIDE(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

+52 −8
Original line number Diff line number Diff line
@@ -161,16 +161,60 @@ static const u32 ipa_reg_idle_indication_cfg_fmask[] = { 


IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220);



IPA_REG_STRIDE(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,

static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,

		      0x00000400, 0x0020);



IPA_REG_STRIDE(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,

static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,

		      0x00000404, 0x0020);



IPA_REG_STRIDE(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,

static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,

		      0x00000500, 0x0020);



IPA_REG_STRIDE(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,

static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,

		      0x00000504, 0x0020);



IPA_REG_STRIDE(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);

drivers/net/ipa/reg/ipa_reg-v4.11.c

+52 −8
Original line number Diff line number Diff line
@@ -218,16 +218,60 @@ static const u32 ipa_reg_timers_pulse_gran_cfg_fmask[] = { 


IPA_REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);



IPA_REG_STRIDE(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,

static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,

		      0x00000400, 0x0020);



IPA_REG_STRIDE(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,

static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,

		      0x00000404, 0x0020);



IPA_REG_STRIDE(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,

static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,

		      0x00000500, 0x0020);



IPA_REG_STRIDE(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,

static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {

	[X_MIN_LIM]					= GENMASK(5, 0),

						/* Bits 6-7 reserved */

	[X_MAX_LIM]					= GENMASK(13, 8),

						/* Bits 14-15 reserved */

	[Y_MIN_LIM]					= GENMASK(21, 16),

						/* Bits 22-23 reserved */

	[Y_MAX_LIM]					= GENMASK(29, 24),

						/* Bits 30-31 reserved */

};



IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,

		      0x00000504, 0x0020);



IPA_REG_STRIDE(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);