Commit 4428673b authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-joerg/arm-smmu/bindings' into for-joerg/arm-smmu/updates 

SMMUv2 DT binding additions, including a generic Qualcomm compatible
string ("qcom,smmu-500") which will hopefully spell the end for
pointless SoC-specific additions in future.

* for-joerg/arm-smmu/bindings:
  iommu/arm-smmu-qcom: Add SM6350 SMMUv2
  dt-bindings: arm-smmu: Add SM6350 GPU SMMUv2
  iommu/arm-smmu-qcom: Add generic qcom,smmu-500 match entry
  iommu/arm-smmu-qcom: Stop using mmu500 reset for v2 MMUs
  iommu/arm-smmu-qcom: Merge table from arm-smmu-qcom-debug into match data
  iommu/arm-smmu-qcom: provide separate implementation for SDM845-smmu-500
  iommu/arm-smmu-qcom: Move the qcom,adreno-smmu check into qcom_smmu_create
  iommu/arm-smmu-qcom: Move implementation data into match data
  dt-bindings: arm-smmu: Add generic qcom,smmu-500 bindings
  dt-bindings: arm-smmu: add special case for Google Cheza platform
  dt-bindings: arm-smmu: fix clocks/clock-names schema
  dt-bindings: arm-smmu: Add missing Qualcomm SMMU compatibles
  dt-bindings: iommu: arm-smmu: add sdm670 compatible
  iommu/arm-smmu-qcom: Add SM6115 support
  dt-bindings: arm-smmu: Add compatible for Qualcomm SM6115
  drivers: arm-smmu-impl: Add QDU1000 and QRU1000 iommu implementation
  dt-bindings: arm-smmu: Add 'compatible' for QDU1000 and QRU1000
parents f87f6e5b 3811a728

Documentation/devicetree/bindings/iommu/arm,smmu.yaml

+169 −9
Original line number Diff line number Diff line
@@ -28,19 +28,50 @@ properties: 
          - enum:

              - qcom,msm8996-smmu-v2

              - qcom,msm8998-smmu-v2

              - qcom,sdm630-smmu-v2

          - const: qcom,smmu-v2



      - description: Qcom SoCs implementing "arm,mmu-500"

      - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"

        items:

          - enum:

              - qcom,qcm2290-smmu-500

              - qcom,qdu1000-smmu-500

              - qcom,sc7180-smmu-500

              - qcom,sc7280-smmu-500

              - qcom,sc8180x-smmu-500

              - qcom,sc8280xp-smmu-500

              - qcom,sdm670-smmu-500

              - qcom,sdm845-smmu-500

              - qcom,sm6115-smmu-500

              - qcom,sm6350-smmu-500

              - qcom,sm6375-smmu-500

              - qcom,sm8150-smmu-500

              - qcom,sm8250-smmu-500

              - qcom,sm8350-smmu-500

              - qcom,sm8450-smmu-500

          - const: qcom,smmu-500

          - const: arm,mmu-500



      - description: Qcom SoCs implementing "arm,mmu-500" (non-qcom implementation)

        deprecated: true

        items:

          - enum:

              - qcom,sdx55-smmu-500

              - qcom,sdx65-smmu-500

          - const: arm,mmu-500



      - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)

        deprecated: true

        items:

          # Do not add additional SoC to this list. Instead use two previous lists.

          - enum:

              - qcom,qcm2290-smmu-500

              - qcom,sc7180-smmu-500

              - qcom,sc7280-smmu-500

              - qcom,sc8180x-smmu-500

              - qcom,sc8280xp-smmu-500

              - qcom,sdm845-smmu-500

              - qcom,sm6115-smmu-500

              - qcom,sm6350-smmu-500

              - qcom,sm6375-smmu-500

              - qcom,sm8150-smmu-500
@@ -48,13 +79,28 @@ properties: 
              - qcom,sm8350-smmu-500

              - qcom,sm8450-smmu-500

          - const: arm,mmu-500



      - description: Qcom Adreno GPUs implementing "arm,smmu-500"

        items:

          - enum:

              - qcom,sc7280-smmu-500

              - qcom,sm8250-smmu-500

          - const: qcom,adreno-smmu

          - const: arm,mmu-500

      - description: Qcom Adreno GPUs implementing "arm,smmu-v2"

        items:

          - enum:

              - qcom,msm8996-smmu-v2

              - qcom,sc7180-smmu-v2

              - qcom,sdm630-smmu-v2

              - qcom,sdm845-smmu-v2

              - qcom,sm6350-smmu-v2

          - const: qcom,adreno-smmu

          - const: qcom,smmu-v2

      - description: Qcom Adreno GPUs on Google Cheza platform

        items:

          - const: qcom,sdm845-smmu-v2

          - const: qcom,smmu-v2

      - description: Marvell SoCs implementing "arm,mmu-500"

        items:

          - const: marvell,ap806-smmu-500
@@ -147,16 +193,12 @@ properties: 
      present in such cases.



  clock-names:

    items:

      - const: bus

      - const: iface

    minItems: 1

    maxItems: 7



  clocks:

    items:

      - description: bus clock required for downstream bus access and for the

          smmu ptw

      - description: interface clock required to access smmu's registers

          through the TCU's programming interface.

    minItems: 1

    maxItems: 7



  power-domains:

    maxItems: 1
@@ -206,6 +248,124 @@ allOf: 
        reg:

          maxItems: 1



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,msm8998-smmu-v2

              - qcom,sdm630-smmu-v2

    then:

      anyOf:

        - properties:

            clock-names:

              items:

                - const: bus

            clocks:

              items:

                - description: bus clock required for downstream bus access and for

                    the smmu ptw

        - properties:

            clock-names:

              items:

                - const: iface

                - const: mem

                - const: mem_iface

            clocks:

              items:

                - description: interface clock required to access smmu's registers

                    through the TCU's programming interface.

                - description: bus clock required for memory access

                - description: bus clock required for GPU memory access

        - properties:

            clock-names:

              items:

                - const: iface-mm

                - const: iface-smmu

                - const: bus-mm

                - const: bus-smmu

            clocks:

              items:

                - description: interface clock required to access mnoc's registers

                    through the TCU's programming interface.

                - description: interface clock required to access smmu's registers

                    through the TCU's programming interface.

                - description: bus clock required for downstream bus access

                - description: bus clock required for the smmu ptw



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,msm8996-smmu-v2

              - qcom,sc7180-smmu-v2

              - qcom,sdm845-smmu-v2

    then:

      properties:

        clock-names:

          items:

            - const: bus

            - const: iface



        clocks:

          items:

            - description: bus clock required for downstream bus access and for

                the smmu ptw

            - description: interface clock required to access smmu's registers

                through the TCU's programming interface.



  - if:

      properties:

        compatible:

          contains:

            const: qcom,sc7280-smmu-500

    then:

      properties:

        clock-names:

          items:

            - const: gcc_gpu_memnoc_gfx_clk

            - const: gcc_gpu_snoc_dvm_gfx_clk

            - const: gpu_cc_ahb_clk

            - const: gpu_cc_hlos1_vote_gpu_smmu_clk

            - const: gpu_cc_cx_gmu_clk

            - const: gpu_cc_hub_cx_int_clk

            - const: gpu_cc_hub_aon_clk



        clocks:

          items:

            - description: GPU memnoc_gfx clock

            - description: GPU snoc_dvm_gfx clock

            - description: GPU ahb clock

            - description: GPU hlos1_vote_GPU smmu clock

            - description: GPU cx_gmu clock

            - description: GPU hub_cx_int clock

            - description: GPU hub_aon clock



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sm6350-smmu-v2

              - qcom,sm8150-smmu-500

              - qcom,sm8250-smmu-500

    then:

      properties:

        clock-names:

          items:

            - const: ahb

            - const: bus

            - const: iface



        clocks:

          items:

            - description: bus clock required for AHB bus access

            - description: bus clock required for downstream bus access and for

                the smmu ptw

            - description: interface clock required to access smmu's registers

                through the TCU's programming interface.



examples:

  - |+

    /* SMMU with stream matching or stream indexing */

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

+0 −91
Original line number Diff line number Diff line
@@ -10,16 +10,6 @@ 
#include "arm-smmu.h"

#include "arm-smmu-qcom.h"



enum qcom_smmu_impl_reg_offset {

	QCOM_SMMU_TBU_PWR_STATUS,

	QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,

	QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,

};



struct qcom_smmu_config {

	const u32 *reg_offset;

};



void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)

{

	int ret;
@@ -59,84 +49,3 @@ void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu) 
			tbu_pwr_status, sync_inv_ack, sync_inv_progress);

	}

}
 


/* Implementation Defined Register Space 0 register offsets */

static const u32 qcom_smmu_impl0_reg_offset[] = {

	[QCOM_SMMU_TBU_PWR_STATUS]		= 0x2204,

	[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK]	= 0x25dc,

	[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR]	= 0x2670,

};



static const struct qcom_smmu_config qcm2290_smmu_cfg = {

	.reg_offset = qcom_smmu_impl0_reg_offset,

};



static const struct qcom_smmu_config sc7180_smmu_cfg = {

	.reg_offset = qcom_smmu_impl0_reg_offset,

};



static const struct qcom_smmu_config sc7280_smmu_cfg = {

	.reg_offset = qcom_smmu_impl0_reg_offset,

};



static const struct qcom_smmu_config sc8180x_smmu_cfg = {

	.reg_offset = qcom_smmu_impl0_reg_offset,

};



static const struct qcom_smmu_config sc8280xp_smmu_cfg = {

	.reg_offset = qcom_smmu_impl0_reg_offset,

};



static const struct qcom_smmu_config sm6125_smmu_cfg = {

	.reg_offset = qcom_smmu_impl0_reg_offset,

};



static const struct qcom_smmu_config sm6350_smmu_cfg = {

	.reg_offset = qcom_smmu_impl0_reg_offset,

};



static const struct qcom_smmu_config sm8150_smmu_cfg = {

	.reg_offset = qcom_smmu_impl0_reg_offset,

};



static const struct qcom_smmu_config sm8250_smmu_cfg = {

	.reg_offset = qcom_smmu_impl0_reg_offset,

};



static const struct qcom_smmu_config sm8350_smmu_cfg = {

	.reg_offset = qcom_smmu_impl0_reg_offset,

};



static const struct qcom_smmu_config sm8450_smmu_cfg = {

	.reg_offset = qcom_smmu_impl0_reg_offset,

};



static const struct of_device_id __maybe_unused qcom_smmu_impl_debug_match[] = {

	{ .compatible = "qcom,msm8998-smmu-v2" },

	{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcm2290_smmu_cfg },

	{ .compatible = "qcom,sc7180-smmu-500", .data = &sc7180_smmu_cfg },

	{ .compatible = "qcom,sc7280-smmu-500", .data = &sc7280_smmu_cfg},

	{ .compatible = "qcom,sc8180x-smmu-500", .data = &sc8180x_smmu_cfg },

	{ .compatible = "qcom,sc8280xp-smmu-500", .data = &sc8280xp_smmu_cfg },

	{ .compatible = "qcom,sdm630-smmu-v2" },

	{ .compatible = "qcom,sdm845-smmu-500" },

	{ .compatible = "qcom,sm6125-smmu-500", .data = &sm6125_smmu_cfg},

	{ .compatible = "qcom,sm6350-smmu-500", .data = &sm6350_smmu_cfg},

	{ .compatible = "qcom,sm8150-smmu-500", .data = &sm8150_smmu_cfg },

	{ .compatible = "qcom,sm8250-smmu-500", .data = &sm8250_smmu_cfg },

	{ .compatible = "qcom,sm8350-smmu-500", .data = &sm8350_smmu_cfg },

	{ .compatible = "qcom,sm8450-smmu-500", .data = &sm8450_smmu_cfg },

	{ }

};



const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu)

{

	const struct of_device_id *match;

	const struct device_node *np = smmu->dev->of_node;



	match = of_match_node(qcom_smmu_impl_debug_match, np);

	if (!match)

		return NULL;



	return match->data;

}

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c

+114 −43
Original line number Diff line number Diff line
@@ -361,6 +361,8 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) 
{

	int ret;



	arm_mmu500_reset(smmu);



	/*

	 * To address performance degradation in non-real time clients,

	 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
@@ -374,41 +376,67 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) 
	return ret;

}



static int qcom_smmu500_reset(struct arm_smmu_device *smmu)

{

	const struct device_node *np = smmu->dev->of_node;



	arm_mmu500_reset(smmu);



	if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))

		return qcom_sdm845_smmu500_reset(smmu);

static const struct arm_smmu_impl qcom_smmu_v2_impl = {

	.init_context = qcom_smmu_init_context,

	.cfg_probe = qcom_smmu_cfg_probe,

	.def_domain_type = qcom_smmu_def_domain_type,

	.write_s2cr = qcom_smmu_write_s2cr,

	.tlb_sync = qcom_smmu_tlb_sync,

};



	return 0;

}

static const struct arm_smmu_impl qcom_smmu_500_impl = {

	.init_context = qcom_smmu_init_context,

	.cfg_probe = qcom_smmu_cfg_probe,

	.def_domain_type = qcom_smmu_def_domain_type,

	.reset = arm_mmu500_reset,

	.write_s2cr = qcom_smmu_write_s2cr,

	.tlb_sync = qcom_smmu_tlb_sync,

};



static const struct arm_smmu_impl qcom_smmu_impl = {

static const struct arm_smmu_impl sdm845_smmu_500_impl = {

	.init_context = qcom_smmu_init_context,

	.cfg_probe = qcom_smmu_cfg_probe,

	.def_domain_type = qcom_smmu_def_domain_type,

	.reset = qcom_smmu500_reset,

	.reset = qcom_sdm845_smmu500_reset,

	.write_s2cr = qcom_smmu_write_s2cr,

	.tlb_sync = qcom_smmu_tlb_sync,

};



static const struct arm_smmu_impl qcom_adreno_smmu_impl = {

static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = {

	.init_context = qcom_adreno_smmu_init_context,

	.def_domain_type = qcom_smmu_def_domain_type,

	.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,

	.write_sctlr = qcom_adreno_smmu_write_sctlr,

	.tlb_sync = qcom_smmu_tlb_sync,

};



static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = {

	.init_context = qcom_adreno_smmu_init_context,

	.def_domain_type = qcom_smmu_def_domain_type,

	.reset = qcom_smmu500_reset,

	.reset = arm_mmu500_reset,

	.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,

	.write_sctlr = qcom_adreno_smmu_write_sctlr,

	.tlb_sync = qcom_smmu_tlb_sync,

};



static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,

		const struct arm_smmu_impl *impl)

		const struct qcom_smmu_match_data *data)

{

	const struct device_node *np = smmu->dev->of_node;

	const struct arm_smmu_impl *impl;

	struct qcom_smmu *qsmmu;



	if (!data)

		return ERR_PTR(-EINVAL);



	if (np && of_device_is_compatible(np, "qcom,adreno-smmu"))

		impl = data->adreno_impl;

	else

		impl = data->impl;



	if (!impl)

		return smmu;



	/* Check to make sure qcom_scm has finished probing */

	if (!qcom_scm_is_available())

		return ERR_PTR(-EPROBE_DEFER);
@@ -418,27 +446,77 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, 
		return ERR_PTR(-ENOMEM);



	qsmmu->smmu.impl = impl;

	qsmmu->cfg = qcom_smmu_impl_data(smmu);

	qsmmu->cfg = data->cfg;



	return &qsmmu->smmu;

}



/* Implementation Defined Register Space 0 register offsets */

static const u32 qcom_smmu_impl0_reg_offset[] = {

	[QCOM_SMMU_TBU_PWR_STATUS]		= 0x2204,

	[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK]	= 0x25dc,

	[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR]	= 0x2670,

};



static const struct qcom_smmu_config qcom_smmu_impl0_cfg = {

	.reg_offset = qcom_smmu_impl0_reg_offset,

};



/*

 * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,

 * there are not enough context banks.

 */

static const struct qcom_smmu_match_data msm8996_smmu_data = {

	.impl = NULL,

	.adreno_impl = &qcom_adreno_smmu_v2_impl,

};



static const struct qcom_smmu_match_data qcom_smmu_v2_data = {

	.impl = &qcom_smmu_v2_impl,

	.adreno_impl = &qcom_adreno_smmu_v2_impl,

};



static const struct qcom_smmu_match_data sdm845_smmu_500_data = {

	.impl = &sdm845_smmu_500_impl,

	/*

	 * No need for adreno impl here. On sdm845 the Adreno SMMU is handled

	 * by the separate sdm845-smmu-v2 device.

	 */

	/* Also no debug configuration. */

};



static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {

	.impl = &qcom_smmu_500_impl,

	.adreno_impl = &qcom_adreno_smmu_500_impl,

	.cfg = &qcom_smmu_impl0_cfg,

};



/*

 * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need

 * special handling and can not be covered by the qcom,smmu-500 entry.

 */

static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {

	{ .compatible = "qcom,msm8998-smmu-v2" },

	{ .compatible = "qcom,qcm2290-smmu-500" },

	{ .compatible = "qcom,sc7180-smmu-500" },

	{ .compatible = "qcom,sc7280-smmu-500" },

	{ .compatible = "qcom,sc8180x-smmu-500" },

	{ .compatible = "qcom,sc8280xp-smmu-500" },

	{ .compatible = "qcom,sdm630-smmu-v2" },

	{ .compatible = "qcom,sdm845-smmu-500" },

	{ .compatible = "qcom,sm6125-smmu-500" },

	{ .compatible = "qcom,sm6350-smmu-500" },

	{ .compatible = "qcom,sm6375-smmu-500" },

	{ .compatible = "qcom,sm8150-smmu-500" },

	{ .compatible = "qcom,sm8250-smmu-500" },

	{ .compatible = "qcom,sm8350-smmu-500" },

	{ .compatible = "qcom,sm8450-smmu-500" },

	{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },

	{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },

	{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data  },

	{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },

	{ .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },

	{ .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },

	{ .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},

	{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },

	{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ }

};
@@ -453,26 +531,19 @@ static struct acpi_platform_list qcom_acpi_platlist[] = { 
struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)

{

	const struct device_node *np = smmu->dev->of_node;

	const struct of_device_id *match;



#ifdef CONFIG_ACPI

	if (np == NULL) {

		/* Match platform for ACPI boot */

		if (acpi_match_platform_list(qcom_acpi_platlist) >= 0)

			return qcom_smmu_create(smmu, &qcom_smmu_impl);

			return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data);

	}

#endif



	/*

	 * Do not change this order of implementation, i.e., first adreno

	 * smmu impl and then apss smmu since we can have both implementing

	 * arm,mmu-500 in which case we will miss setting adreno smmu specific

	 * features if the order is changed.

	 */

	if (of_device_is_compatible(np, "qcom,adreno-smmu"))

		return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);



	if (of_match_node(qcom_smmu_impl_of_match, np))

		return qcom_smmu_create(smmu, &qcom_smmu_impl);

	match = of_match_node(qcom_smmu_impl_of_match, np);

	if (match)

		return qcom_smmu_create(smmu, match->data);



	return smmu;

}

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h

+16 −5
Original line number Diff line number Diff line
@@ -14,15 +14,26 @@ struct qcom_smmu { 
	u32 stall_enabled;

};



enum qcom_smmu_impl_reg_offset {

	QCOM_SMMU_TBU_PWR_STATUS,

	QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,

	QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,

};



struct qcom_smmu_config {

	const u32 *reg_offset;

};



struct qcom_smmu_match_data {

	const struct qcom_smmu_config *cfg;

	const struct arm_smmu_impl *impl;

	const struct arm_smmu_impl *adreno_impl;

};



#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG

void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu);

const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu);

#else

static inline void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu) { }

static inline const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu)

{

	return NULL;

}

#endif



#endif /* _ARM_SMMU_QCOM_H */