Commit 43f0b562 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:
 "Minor fixes all over, ranging from typos to tests to errata
  workarounds:

   - Fix possible memory hotplug failure with KASLR

   - Fix FFR value in SVE kselftest

   - Fix backtraces reported in /proc/$pid/stack

   - Disable broken CnP implementation on NVIDIA Carmel

   - Typo fixes and ACPI documentation clarification

   - Fix some W=1 warnings"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: kernel: disable CNP on Carmel
  arm64/process.c: fix Wmissing-prototypes build warnings
  kselftest/arm64: sve: Do not use non-canonical FFR register value
  arm64: mm: correct the inside linear map range during hotplug check
  arm64: kdump: update ppos when reading elfcorehdr
  arm64: cpuinfo: Fix a typo
  Documentation: arm64/acpi : clarify arm64 support of IBFT
  arm64: stacktrace: don't trace arch_stack_walk()
  arm64: csum: cast to the proper type
parents 7aae5432 20109a85

Documentation/arm64/acpi_object_usage.rst

+5 −5
Original line number Diff line number Diff line
@@ -17,12 +17,12 @@ For ACPI on arm64, tables also fall into the following categories: 


       -  Recommended: BERT, EINJ, ERST, HEST, PCCT, SSDT



       -  Optional: BGRT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT, IORT,

          MCHI, MPST, MSCT, NFIT, PMTT, RASF, SBST, SLIT, SPMI, SRAT, STAO,

	  TCPA, TPM2, UEFI, XENV

       -  Optional: BGRT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT, IBFT,

          IORT, MCHI, MPST, MSCT, NFIT, PMTT, RASF, SBST, SLIT, SPMI, SRAT,

          STAO, TCPA, TPM2, UEFI, XENV



       -  Not supported: BOOT, DBGP, DMAR, ETDT, HPET, IBFT, IVRS, LPIT,

          MSDM, OEMx, PSDT, RSDT, SLIC, WAET, WDAT, WDRT, WPBT

       -  Not supported: BOOT, DBGP, DMAR, ETDT, HPET, IVRS, LPIT, MSDM, OEMx,

          PSDT, RSDT, SLIC, WAET, WDAT, WDRT, WPBT



====== ========================================================================

Table  Usage for ARMv8 Linux

Documentation/arm64/silicon-errata.rst

+3 −0
Original line number Diff line number Diff line
@@ -130,6 +130,9 @@ stable kernels. 
| Marvell        | ARM-MMU-500     | #582743         | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| NVIDIA         | Carmel Core     | N/A             | NVIDIA_CARMEL_CNP_ERRATUM   |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585         |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -810,6 +810,16 @@ config QCOM_FALKOR_ERRATUM_E1041 


	  If unsure, say Y.



config NVIDIA_CARMEL_CNP_ERRATUM

	bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"

	default y

	help

	  If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not

	  invalidate shared TLB entries installed by a different core, as it would

	  on standard ARM cores.



	  If unsure, say Y.



config SOCIONEXT_SYNQUACER_PREITS

	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"

	default y

arch/arm64/include/asm/checksum.h

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) 
	} while (--n > 0);



	sum += ((sum >> 32) | (sum << 32));

	return csum_fold((__force u32)(sum >> 32));

	return csum_fold((__force __wsum)(sum >> 32));

}

#define ip_fast_csum ip_fast_csum

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -66,7 +66,8 @@ 
#define ARM64_WORKAROUND_1508412		58

#define ARM64_HAS_LDAPR				59

#define ARM64_KVM_PROTECTED_MODE		60

#define ARM64_WORKAROUND_NVIDIA_CARMEL_CNP	61



#define ARM64_NCAPS				61

#define ARM64_NCAPS				62



#endif /* __ASM_CPUCAPS_H */