Commit 20109a85 authored Mar 23, 2021 by Rich Wiley Committed by Will Deacon Mar 25, 2021

arm64: kernel: disable CNP on Carmel



On NVIDIA Carmel cores, CNP behaves differently than it does on standard
ARM cores. On Carmel, if two cores have CNP enabled and share an L2 TLB
entry created by core0 for a specific ASID, a non-shareable TLBI from
core1 may still see the shared entry. On standard ARM cores, that TLBI
will invalidate the shared entry as well.

This causes issues with patchsets that attempt to do local TLBIs based
on cpumasks instead of broadcast TLBIs. Avoid these issues by disabling
CNP support for NVIDIA Carmel cores.

Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Link: https://lore.kernel.org/r/20210324002809.30271-1-rwiley@nvidia.com


[will: Fix pre-existing whitespace issue]
Signed-off-by: Will Deacon <will@kernel.org>

parent baa96377

Documentation/arm64/silicon-errata.rst

+3 −0

Original line number	Diff line number	Diff line
		@@ -130,6 +130,9 @@ stable kernels.
		\| Marvell \| ARM-MMU-500 \| #582743 \| N/A \|
		+----------------+-----------------+-----------------+-----------------------------+
		+----------------+-----------------+-----------------+-----------------------------+
		\| NVIDIA \| Carmel Core \| N/A \| NVIDIA_CARMEL_CNP_ERRATUM \|
		+----------------+-----------------+-----------------+-----------------------------+
		+----------------+-----------------+-----------------+-----------------------------+
		\| Freescale/NXP \| LS2080A/LS1043A \| A-008585 \| FSL_ERRATUM_A008585 \|
		+----------------+-----------------+-----------------+-----------------------------+
		+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+10 −0

Original line number	Diff line number	Diff line
		@@ -810,6 +810,16 @@ config QCOM_FALKOR_ERRATUM_E1041

		If unsure, say Y.

		config NVIDIA_CARMEL_CNP_ERRATUM
		bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
		default y
		help
		If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
		invalidate shared TLB entries installed by a different core, as it would
		on standard ARM cores.

		If unsure, say Y.

		config SOCIONEXT_SYNQUACER_PREITS
		bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
		default y

arch/arm64/include/asm/cpucaps.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -66,7 +66,8 @@
		#define ARM64_WORKAROUND_1508412 58
		#define ARM64_HAS_LDAPR 59
		#define ARM64_KVM_PROTECTED_MODE 60
		#define ARM64_WORKAROUND_NVIDIA_CARMEL_CNP 61

		#define ARM64_NCAPS 61
		#define ARM64_NCAPS 62

		#endif /* __ASM_CPUCAPS_H */

arch/arm64/kernel/cpu_errata.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -525,6 +525,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
		0, 0,
		1, 0),
		},
		#endif
		#ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM
		{
		/* NVIDIA Carmel */
		.desc = "NVIDIA Carmel CNP erratum",
		.capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
		ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
		},
		#endif
		{
		}

arch/arm64/kernel/cpufeature.c

+4 −1

Original line number	Diff line number	Diff line
		@@ -1324,6 +1324,9 @@ has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
		if (is_kdump_kernel())
		return false;

		if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
		return false;

		return has_cpuid_feature(entry, scope);
		}