Commit 43476605 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf_urgent_for_v6.1_rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull perf fixes from Borislav Petkov:

 - Rename a perf memory level event define to denote it is of CXL type

 - Add Alder and Raptor Lakes support to RAPL

 - Make sure raw sample data is output with tracepoints

* tag 'perf_urgent_for_v6.1_rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/mem: Rename PERF_MEM_LVLNUM_EXTN_MEM to PERF_MEM_LVLNUM_CXL
  perf/x86/rapl: Add support for Intel Raptor Lake
  perf/x86/rapl: Add support for Intel AlderLake-N
  perf: Fix missing raw data on tracepoint events
parents c96bb958 cb6c18b5
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+1 −1
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@@ -801,7 +801,7 @@ static void perf_ibs_get_mem_lvl(union ibs_op_data2 *op_data2,
	/* Extension Memory */
	if (ibs_caps & IBS_CAPS_ZEN4 &&
	    ibs_data_src == IBS_DATA_SRC_EXT_EXT_MEM) {
		data_src->mem_lvl_num = PERF_MEM_LVLNUM_EXTN_MEM;
		data_src->mem_lvl_num = PERF_MEM_LVLNUM_CXL;
		if (op_data2->rmt_node) {
			data_src->mem_remote = PERF_MEM_REMOTE_REMOTE;
			/* IBS doesn't provide Remote socket detail */
+4 −0
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@@ -806,7 +806,11 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = {
	X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE,		&model_skl),
	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&model_skl),
	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&model_skl),
	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,		&model_skl),
	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	&model_spr),
	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,		&model_skl),
	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,	&model_skl),
	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S,	&model_skl),
	{},
};
MODULE_DEVICE_TABLE(x86cpu, rapl_model_match);
+1 −1
Original line number Diff line number Diff line
@@ -1337,7 +1337,7 @@ union perf_mem_data_src {
#define PERF_MEM_LVLNUM_L3	0x03 /* L3 */
#define PERF_MEM_LVLNUM_L4	0x04 /* L4 */
/* 5-0x8 available */
#define PERF_MEM_LVLNUM_EXTN_MEM 0x09 /* Extension memory */
#define PERF_MEM_LVLNUM_CXL	0x09 /* CXL */
#define PERF_MEM_LVLNUM_IO	0x0a /* I/O */
#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
#define PERF_MEM_LVLNUM_LFB	0x0c /* LFB */
+1 −0
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@@ -9846,6 +9846,7 @@ void perf_tp_event(u16 event_type, u64 count, void *record, int entry_size,

	perf_sample_data_init(&data, 0, 0);
	data.raw = &raw;
	data.sample_flags |= PERF_SAMPLE_RAW;

	perf_trace_buf_update(record, event_type);