Commit cb6c18b5 authored by Ravi Bangoria's avatar Ravi Bangoria Committed by Peter Zijlstra
Browse files

perf/mem: Rename PERF_MEM_LVLNUM_EXTN_MEM to PERF_MEM_LVLNUM_CXL 



PERF_MEM_LVLNUM_EXTN_MEM was introduced to cover CXL devices but it's
bit ambiguous name and also not generic enough to cover cxl.cache and
cxl.io devices. Rename it to PERF_MEM_LVLNUM_CXL to be more specific.

Signed-off-by: default avatarRavi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/f6268268-b4e9-9ed6-0453-65792644d953@amd.com
parent eff98a74

arch/x86/events/amd/ibs.c

+1 −1
Original line number Diff line number Diff line
@@ -801,7 +801,7 @@ static void perf_ibs_get_mem_lvl(union ibs_op_data2 *op_data2, 
	/* Extension Memory */

	if (ibs_caps & IBS_CAPS_ZEN4 &&

	    ibs_data_src == IBS_DATA_SRC_EXT_EXT_MEM) {

		data_src->mem_lvl_num = PERF_MEM_LVLNUM_EXTN_MEM;

		data_src->mem_lvl_num = PERF_MEM_LVLNUM_CXL;

		if (op_data2->rmt_node) {

			data_src->mem_remote = PERF_MEM_REMOTE_REMOTE;

			/* IBS doesn't provide Remote socket detail */

include/uapi/linux/perf_event.h

+1 −1
Original line number Diff line number Diff line
@@ -1337,7 +1337,7 @@ union perf_mem_data_src { 
#define PERF_MEM_LVLNUM_L3	0x03 /* L3 */

#define PERF_MEM_LVLNUM_L4	0x04 /* L4 */

/* 5-0x8 available */

#define PERF_MEM_LVLNUM_EXTN_MEM 0x09 /* Extension memory */

#define PERF_MEM_LVLNUM_CXL	0x09 /* CXL */

#define PERF_MEM_LVLNUM_IO	0x0a /* I/O */

#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */

#define PERF_MEM_LVLNUM_LFB	0x0c /* LFB */