Commit 4222744d authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-starfive', 'clk-ti', 'clk-terminate' and 'clk-cleanup' into clk-next

 - Audio clks on StarFive JH7100 RISC-V SoC
 - Terminate arrays with sentinels and make that clearer
 - Cleanup SPDX tags
 - Fix typos in comments

* clk-starfive:
  clk: starfive: Add JH7100 audio clock driver
  clk: starfive: jh7100: Support more clock types
  clk: starfive: jh7100: Make hw clock implementation reusable
  dt-bindings: clock: Add starfive,jh7100-audclk bindings
  dt-bindings: clock: Add JH7100 audio clock definitions
  clk: starfive: jh7100: Handle audio_div clock properly
  clk: starfive: jh7100: Don't round divisor up twice

* clk-ti:
  clk: ti: Drop legacy compatibility clocks for dra7
  clk: ti: Drop legacy compatibility clocks for am4
  clk: ti: Drop legacy compatibility clocks for am3
  clk: ti: Update component clocks to use ti_dt_clk_name()
  clk: ti: Update pll and clockdomain clocks to use ti_dt_clk_name()
  clk: ti: Add ti_dt_clk_name() helper to use clock-output-names
  clk: ti: Use clock-output-names for clkctrl
  clk: ti: Add ti_find_clock_provider() to use clock-output-names
  clk: ti: Optionally parse IO address from parent clock node
  clk: ti: Preserve node in ti_dt_clocks_register()
  clk: ti: Constify clkctrl_name

* clk-terminate:
  clk: actions: Make sentinel elements more obvious
  clk: clps711x: Terminate clk_div_table with sentinel element
  clk: hisilicon: Terminate clk_div_table with sentinel element
  clk: loongson1: Terminate clk_div_table with sentinel element
  clk: actions: Terminate clk_div_table with sentinel element

* clk-cleanup:
  clk: zynq: Update the parameters to zynq_clk_register_periph_clk
  clk: zynq: trivial warning fix
  clk: qcom: sm6125-gcc: fix typos in comments
  clk: ti: clkctrl: fix typos in comments
  clk: COMMON_CLK_LAN966X should depend on SOC_LAN966
  clk: Use of_device_get_match_data()
  clk: bcm2835: Remove unused variable
  clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driver
  clk: cleanup comments
  clk: socfpga: cleanup spdx tags
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+57 −0
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JH7100 Audio Clock Generator

maintainers:
  - Emil Renner Berthing <kernel@esmil.dk>

properties:
  compatible:
    const: starfive,jh7100-audclk

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Audio source clock
      - description: External 12.288MHz clock
      - description: Domain 7 AHB bus clock

  clock-names:
    items:
      - const: audio_src
      - const: audio_12288
      - const: dom7ahb_bus

  '#clock-cells':
    const: 1
    description:
      See <dt-bindings/clock/starfive-jh7100-audio.h> for valid indices.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/starfive-jh7100.h>

    clock-controller@10480000 {
            compatible = "starfive,jh7100-audclk";
            reg = <0x10480000 0x10000>;
            clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
                     <&clkgen JH7100_CLK_AUDIO_12288>,
                     <&clkgen JH7100_CLK_DOM7AHB_BUS>;
            clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
            #clock-cells = <1>;
    };
+4 −4
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@@ -18430,12 +18430,12 @@ M: Ion Badulescu <ionut@badula.org>
S:	Odd Fixes
F:	drivers/net/ethernet/adaptec/starfire*
STARFIVE JH7100 CLOCK DRIVER
STARFIVE JH7100 CLOCK DRIVERS
M:	Emil Renner Berthing <kernel@esmil.dk>
S:	Maintained
F:	Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
F:	drivers/clk/starfive/clk-starfive-jh7100.c
F:	include/dt-bindings/clock/starfive-jh7100.h
F:	Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml
F:	drivers/clk/starfive/clk-starfive-jh7100*
F:	include/dt-bindings/clock/starfive-jh7100*.h
STARFIVE JH7100 PINCTRL DRIVER
M:	Emil Renner Berthing <kernel@esmil.dk>
+1 −0
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@@ -232,6 +232,7 @@ config COMMON_CLK_GEMINI

config COMMON_CLK_LAN966X
	bool "Generic Clock Controller driver for LAN966X SoC"
	depends on SOC_LAN966 || COMPILE_TEST
	help
	  This driver provides support for Generic Clock Controller(GCK) on
	  LAN966X SoC. GCK generates and supplies clock to various peripherals
+8 −8
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@

static const struct clk_pll_table clk_audio_pll_table[] = {
	{ 0, 45158400 }, { 1, 49152000 },
	{ 0, 0 },
	{ /* sentinel */ }
};

/* pll clocks */
@@ -138,46 +138,46 @@ static struct clk_factor_table sd_factor_table[] = {
	{ 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
	{ 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
	{ 280, 1, 25 * 128 },
	{ 0, 0, 0 },
	{ /* sentinel */ }
};

static struct clk_factor_table de_factor_table[] = {
	{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
	{ 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
	{ 8, 1, 12 },
	{ 0, 0, 0 },
	{ /* sentinel */ }
};

static struct clk_factor_table hde_factor_table[] = {
	{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
	{ 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
	{ 0, 0, 0 },
	{ /* sentinel */ }
};

static struct clk_div_table rmii_ref_div_table[] = {
	{ 0, 4 }, { 1, 10 },
	{ 0, 0 },
	{ /* sentinel */ }
};

static struct clk_div_table std12rate_div_table[] = {
	{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
	{ 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
	{ 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
	{ 0, 0 },
	{ /* sentinel */ }
};

static struct clk_div_table i2s_div_table[] = {
	{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
	{ 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
	{ 8, 24 },
	{ 0, 0 },
	{ /* sentinel */ }
};

static struct clk_div_table nand_div_table[] = {
	{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 },
	{ 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
	{ 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
	{ 0, 0 },
	{ /* sentinel */ }
};

/* mux clock */
+10 −7
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@

static struct clk_pll_table clk_audio_pll_table[] = {
	{0, 45158400}, {1, 49152000},
	{0, 0},
	{ /* sentinel */ }
};

static struct clk_pll_table clk_cvbs_pll_table[] = {
@@ -82,7 +82,8 @@ static struct clk_pll_table clk_cvbs_pll_table[] = {
	{33, 35 * 12000000}, {34, 36 * 12000000}, {35, 37 * 12000000},
	{36, 38 * 12000000}, {37, 39 * 12000000}, {38, 40 * 12000000},
	{39, 41 * 12000000}, {40, 42 * 12000000}, {41, 43 * 12000000},
	{42, 44 * 12000000}, {43, 45 * 12000000}, {0, 0},
	{42, 44 * 12000000}, {43, 45 * 12000000},
	{ /* sentinel */ }
};

/* pll clocks */
@@ -137,7 +138,7 @@ static struct clk_factor_table sd_factor_table[] = {
	{276, 1, 21 * 128}, {277, 1, 22 * 128}, {278, 1, 23 * 128}, {279, 1, 24 * 128},
	{280, 1, 25 * 128}, {281, 1, 26 * 128},

	{0, 0},
	{ /* sentinel */ }
};

static struct clk_factor_table lcd_factor_table[] = {
@@ -150,18 +151,19 @@ static struct clk_factor_table lcd_factor_table[] = {
	{256, 1, 1 * 7}, {257, 1, 2 * 7}, {258, 1, 3 * 7}, {259, 1, 4 * 7},
	{260, 1, 5 * 7}, {261, 1, 6 * 7}, {262, 1, 7 * 7}, {263, 1, 8 * 7},
	{264, 1, 9 * 7}, {265, 1, 10 * 7}, {266, 1, 11 * 7}, {267, 1, 12 * 7},
	{0, 0},
	{ /* sentinel */ }
};

static struct clk_div_table hdmia_div_table[] = {
	{0, 1},   {1, 2},   {2, 3},   {3, 4},
	{4, 6},   {5, 8},   {6, 12},  {7, 16},
	{8, 24},
	{0, 0},
	{ /* sentinel */ }
};

static struct clk_div_table rmii_div_table[] = {
	{0, 4},   {1, 10},
	{ /* sentinel */ }
};

/* divider clocks */
@@ -178,13 +180,14 @@ static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2,
static struct clk_factor_table de_factor_table[] = {
	{0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
	{4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
	{8, 1, 12}, {0, 0, 0},
	{8, 1, 12},
	{ /* sentinel */ }
};

static struct clk_factor_table hde_factor_table[] = {
	{0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
	{4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
	{0, 0, 0},
	{ /* sentinel */ }
};

/* gate clocks */
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