Commit 3f614ab5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'irq-core-2023-04-24' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull interrupt updates from Thomas Gleixner:
 "Core:

   - Add tracepoints for tasklet callbacks which makes it possible to
     analyze individual tasklet functions instead of guess working from
     the overall duration of tasklet processing

   - Ensure that secondary interrupt threads have their affinity
     adjusted correctly

  Drivers:

   - A large rework of the RISC-V IPI management to prepare for a new
     RISC-V interrupt architecture

   - Small fixes and enhancements all over the place

   - Removal of support for various obsolete hardware platforms and the
     related code"

* tag 'irq-core-2023-04-24' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (21 commits)
  irqchip/st: Remove stih415/stih416 and stid127 platforms support
  irqchip/gic-v3: Add Rockchip 3588001 erratum workaround
  genirq: Update affinity of secondary threads
  softirq: Add trace points for tasklet entry/exit
  irqchip/loongson-pch-pic: Fix pch_pic_acpi_init calling
  irqchip/loongson-pch-pic: Fix registration of syscore_ops
  irqchip/loongson-eiointc: Fix registration of syscore_ops
  irqchip/loongson-eiointc: Fix incorrect use of acpi_get_vec_parent
  irqchip/loongson-eiointc: Fix returned value on parsing MADT
  irqchip/riscv-intc: Add empty irq_eoi() for chained irq handlers
  RISC-V: Use IPIs for remote icache flush when possible
  RISC-V: Use IPIs for remote TLB flush when possible
  RISC-V: Allow marking IPIs as suitable for remote FENCEs
  RISC-V: Treat IPIs as normal Linux IRQs
  irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode
  RISC-V: Clear SIP bit only when using SBI IPI operations
  irqchip/irq-sifive-plic: Add syscore callbacks for hibernation
  irqchip: Use of_property_read_bool() for boolean properties
  irqchip/bcm-6345-l1: Request memory region
  irqchip/gicv3: Workaround for NVIDIA erratum T241-FABRIC-4
  ...
parents 15bbeec0 f37202aa

Documentation/arm64/silicon-errata.rst

+5 −0
Original line number Diff line number Diff line
@@ -172,6 +172,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| NVIDIA         | Carmel Core     | N/A             | NVIDIA_CARMEL_CNP_ERRATUM   |

+----------------+-----------------+-----------------+-----------------------------+

| NVIDIA         | T241 GICv3/4.x  | T241-FABRIC-4   | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585         |

+----------------+-----------------+-----------------+-----------------------------+
@@ -205,6 +207,9 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo4xx Gold    | N/A             | ARM64_ERRATUM_1286807       |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Rockchip       | RK3588          | #3588001        | ROCKCHIP_ERRATUM_3588001    |

+----------------+-----------------+-----------------+-----------------------------+



+----------------+-----------------+-----------------+-----------------------------+

| Fujitsu        | A64FX           | E#010001        | FUJITSU_ERRATUM_010001      |

arch/arm64/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -1150,6 +1150,16 @@ config NVIDIA_CARMEL_CNP_ERRATUM 


	  If unsure, say Y.



config ROCKCHIP_ERRATUM_3588001

	bool "Rockchip 3588001: GIC600 can not support shareability attributes"

	default y

	help

	  The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.

	  This means, that its sharability feature may not be used, even though it

	  is supported by the IP itself.



	  If unsure, say Y.



config SOCIONEXT_SYNQUACER_PREITS

	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"

	default y

arch/riscv/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -63,6 +63,8 @@ config RISCV 
	select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO

	select GENERIC_IDLE_POLL_SETUP

	select GENERIC_IOREMAP if MMU

	select GENERIC_IRQ_IPI if SMP

	select GENERIC_IRQ_IPI_MUX if SMP

	select GENERIC_IRQ_MULTI_HANDLER

	select GENERIC_IRQ_SHOW

	select GENERIC_IRQ_SHOW_LEVEL

arch/riscv/include/asm/irq.h

+4 −0
Original line number Diff line number Diff line
@@ -12,6 +12,10 @@ 


#include <asm-generic/irq.h>



void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void));



struct fwnode_handle *riscv_get_intc_hwnode(void);



extern void __init init_IRQ(void);



#endif /* _ASM_RISCV_IRQ_H */

arch/riscv/include/asm/sbi.h

+7 −2
Original line number Diff line number Diff line
@@ -271,8 +271,7 @@ long sbi_get_marchid(void); 
long sbi_get_mimpid(void);

void sbi_set_timer(uint64_t stime_value);

void sbi_shutdown(void);

void sbi_clear_ipi(void);

int sbi_send_ipi(const struct cpumask *cpu_mask);

void sbi_send_ipi(unsigned int cpu);

int sbi_remote_fence_i(const struct cpumask *cpu_mask);

int sbi_remote_sfence_vma(const struct cpumask *cpu_mask,

			   unsigned long start,
@@ -335,4 +334,10 @@ unsigned long riscv_cached_mvendorid(unsigned int cpu_id); 
unsigned long riscv_cached_marchid(unsigned int cpu_id);

unsigned long riscv_cached_mimpid(unsigned int cpu_id);



#if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI)

void sbi_ipi_init(void);

#else

static inline void sbi_ipi_init(void) { }

#endif



#endif /* _ASM_RISCV_SBI_H */