Commit f37202aa authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'irqchip-6.4' of... 

Merge tag 'irqchip-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip changes from Marc Zyngier:

 - Large RISC-V IPI rework to make way for a new interrupt
   architecture

 - More Loongarch fixes from Lianmin Lv, fixing issues in the so
   called "dual-bridge" systems.

 - Workaround for the nvidia T241 chip that gets confused in
   3 and 4 socket configurations, leading to the GIC
   malfunctionning in some contexts

 - Drop support for non-firmware driven GIC configurarations
   now that the old ARM11MP Cavium board is gone

 - Workaround for the Rockchip 3588 chip that doesn't
   correctly deal with the shareability attributes.

 - Replace uses of of_find_property() with the more appropriate
   of_property_read_bool()

 - Make bcm-6345-l1 request its MMIO region

 - Add suspend support to the SiFive PLIC

 - Drop support for stih415, stih416 and stid127 platforms

Link: https://lore.kernel.org/lkml/20230421132104.3021536-1-maz@kernel.org
parents 80323598 2ff1b083

Documentation/arm64/silicon-errata.rst

+5 −0
Original line number Diff line number Diff line
@@ -172,6 +172,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| NVIDIA         | Carmel Core     | N/A             | NVIDIA_CARMEL_CNP_ERRATUM   |

+----------------+-----------------+-----------------+-----------------------------+

| NVIDIA         | T241 GICv3/4.x  | T241-FABRIC-4   | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585         |

+----------------+-----------------+-----------------+-----------------------------+
@@ -205,6 +207,9 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo4xx Gold    | N/A             | ARM64_ERRATUM_1286807       |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Rockchip       | RK3588          | #3588001        | ROCKCHIP_ERRATUM_3588001    |

+----------------+-----------------+-----------------+-----------------------------+



+----------------+-----------------+-----------------+-----------------------------+

| Fujitsu        | A64FX           | E#010001        | FUJITSU_ERRATUM_010001      |

arch/arm64/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -1150,6 +1150,16 @@ config NVIDIA_CARMEL_CNP_ERRATUM 


	  If unsure, say Y.



config ROCKCHIP_ERRATUM_3588001

	bool "Rockchip 3588001: GIC600 can not support shareability attributes"

	default y

	help

	  The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.

	  This means, that its sharability feature may not be used, even though it

	  is supported by the IP itself.



	  If unsure, say Y.



config SOCIONEXT_SYNQUACER_PREITS

	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"

	default y

arch/riscv/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -63,6 +63,8 @@ config RISCV 
	select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO

	select GENERIC_IDLE_POLL_SETUP

	select GENERIC_IOREMAP if MMU

	select GENERIC_IRQ_IPI if SMP

	select GENERIC_IRQ_IPI_MUX if SMP

	select GENERIC_IRQ_MULTI_HANDLER

	select GENERIC_IRQ_SHOW

	select GENERIC_IRQ_SHOW_LEVEL

arch/riscv/include/asm/irq.h

+4 −0
Original line number Diff line number Diff line
@@ -12,6 +12,10 @@ 


#include <asm-generic/irq.h>



void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void));



struct fwnode_handle *riscv_get_intc_hwnode(void);



extern void __init init_IRQ(void);



#endif /* _ASM_RISCV_IRQ_H */

arch/riscv/include/asm/sbi.h

+7 −2
Original line number Diff line number Diff line
@@ -271,8 +271,7 @@ long sbi_get_marchid(void); 
long sbi_get_mimpid(void);

void sbi_set_timer(uint64_t stime_value);

void sbi_shutdown(void);

void sbi_clear_ipi(void);

int sbi_send_ipi(const struct cpumask *cpu_mask);

void sbi_send_ipi(unsigned int cpu);

int sbi_remote_fence_i(const struct cpumask *cpu_mask);

int sbi_remote_sfence_vma(const struct cpumask *cpu_mask,

			   unsigned long start,
@@ -335,4 +334,10 @@ unsigned long riscv_cached_mvendorid(unsigned int cpu_id); 
unsigned long riscv_cached_marchid(unsigned int cpu_id);

unsigned long riscv_cached_mimpid(unsigned int cpu_id);



#if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI)

void sbi_ipi_init(void);

#else

static inline void sbi_ipi_init(void) { }

#endif



#endif /* _ASM_RISCV_SBI_H */